LPC11A14FBD48/301, NXP Semiconductors, LPC11A14FBD48/301, Datasheet - Page 55

• Manufacturer Part Number: LPC11A14FBD48/301,
• Description: ARM Microcontrollers - MCU CortexM0 32bit 32KB
• Manufacturer: NXP Semiconductors

Specifications of LPC11A14FBD48/301,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11A
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.6 V to 3.6 V
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 250

NXP Semiconductors
LPC11AXX
Product data sheet
Table 15.
T
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] A Fast-mode I
Symbol
t
t
t
HIGH
HD;DAT
SU;DAT
amb
See the I
Parameters are valid over operating temperature range unless otherwise specified.
t
and the acknowledge.
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
V
C
The maximum t
output stage t
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
The maximum t
the maximum of t
the device does not stretch the LOW period (t
data must be valid by the set-up time before it releases the clock.
t
transmission and the acknowledge.
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t
specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
HD;DAT
SU;DAT
=
IH
b

= total capacitance of one bus line in pF.
(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
40
is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
is the data hold time that is measured from the falling edge of SCL; applies to data in transmission

Dynamic characteristic: I
C to +85
2
C-bus specification UM10204 for details.
Parameter
HIGH period of
the SCL clock
data hold time
data set-up
time
f
2
All information provided in this document is subject to legal disclaimers.
is specified at 250 ns. This allows series protection resistors to be connected in between the
C-bus device can be used in a Standard-mode I
HD;DAT
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
VD;DAT

C.
could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than
[2]
Rev. 4 — 30 October 2012
or t
r(max)
VD;ACK
[3][4][8]
[9][10]
+ t
SU;DAT
by a transition time (see UM10204). This maximum must only be met if
2
= 1000 + 250 = 1250 ns (according to the Standard-mode I
C-bus pins
Conditions
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
LOW
) of the SCL signal. If the clock stretches the SCL, the
[1]
32-bit ARM Cortex-M0 microcontroller
2
C-bus system but the requirement t
Min
4.0
0.6
0.26
0
0
0
250
100
50
LPC11Axx
© NXP B.V. 2012. All rights reserved.
Max
-
-
-
-
-
-
-
-
-
f
.
Unit
s
s
s
s
s
s
ns
ns
ns
2
SU;DAT
55 of 84
C-bus
=