LPC11A14FBD48/301, NXP Semiconductors, LPC11A14FBD48/301, Datasheet
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LPC11Axx 32-bit ARM Cortex-M0 microcontroller flash SRAM EEPROM; configurable analog/mixed-signal Rev. 4 — 30 October 2012 1. General description The LPC11Axx are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for ...
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... NXP Semiconductors pins are configurable with a digital input glitch filter for removing glitches with widths less and two pins are configurable for 50 ns glitch filters. GPIO pins can be used as edge and level sensitive interrupt sources. ...
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... NXP Semiconductors Single 3.3 V power supply (2 3.6 V). Temperature range 40 C to +85 C. Available as LQFP48 package, HVQFN33 ( in a very small WLCSP20 package. 3. Applications Power management Industrial control Remote monitoring Point-of-sale Test and measurement equipment ...
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... NXP Semiconductors 4.1 Ordering options Table 2. Ordering options Type number Flash LPC11A02UK 16 kB LPC11A04UK 32 kB LPC11A11FHN33/001 8 kB LPC11A12FHN33/101 16 kB LPC11A12FBD48/101 16 kB LPC11A13FHI33/201 24 kB LPC11A14FHN33/301 32 kB LPC11A14FBD48/301 32 kB LPC11AXX Product data sheet SRAM EEPROM 512 ...
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... NXP Semiconductors 5. Block diagram LPC11Axx HIGH-SPEED GPIO ports GPIO RXD TXD CTS, DCD, DSR, RI RTS, DTR SCLK CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP[2:0] CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 CT32B1_CAP[2:0] CT16B0_MAT[3:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP[2:0] CT16B1_MAT[3:0] 16-bit COUNTER/TIMER 1 CT16B1_CAP[2:0] WINDOWED WATCHDOG SYSTEM CONTROL (1) Open-drain pins. (2) Standard I/O pins. ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. LPC11AXX Product data sheet PIO0_26 1 PIO0_28 2 3 RESET/PIO0_0 4 PIO0_1 V 5 SS(IO) LPC11A12FBD48/101 XTALIN 6 LPC11A14FBD48/301 XTALOUT DD(IO) 9 PIO0_24 PIO0_18 10 PIO1_6 11 PIO1_9 12 Pin configuration LQFP48 package All information provided in this document is subject to legal disclaimers. Rev. 4 — 30 October 2012 ...
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... NXP Semiconductors Fig 3. Fig 4. 6.2 Pin description All functional pins on the LPC11Axx are mapped to GPIO port 0 and port 1 (see The port pins are multiplexed to accommodate more than one function (see The pin function is controlled by the pin’s IOCON register (see the LPC11Axx user manual) ...
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... NXP Semiconductors Table 3. Function System clocks, reset, and wake-up CLKIN CLKOUT XTALIN XTALOUT RESET Serial Wire Debug (SWD) and JTAG TRST TCK TDI TDO TMS SWCLK SWDIO Analog peripherals (ADC, DAC, comparator) ACMP_I1 ACMP_I2 ACMP_I3 ACMP_I4 ACMP_I5 ACMP_O AD0 AD1 LPC11AXX ...
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... NXP Semiconductors Table 3. Function AD2 AD3 AD4 AD5 AD6 AD7 AOUT ATRG0 ATRG1 VDDCMP 2 I C-bus interface SCL SDA SSP0 controller MISO0 MOSI0 SCK0 SSEL0 LPC11AXX Product data sheet Pin multiplexing Type Port Glitch filter Pin I PIO0_8 no (analog) I PIO0_9 no (analog) I PIO0_10 ...
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... NXP Semiconductors Table 3. Function SSP1 controller MISO1 MOSI1 SCK1 SSEL1 USART RXD TXD SCLK CTS RTS DCD DSR DTR LPC11AXX Product data sheet Pin multiplexing Type Port Glitch filter Pin I/O PIO0_14 10 ns PIO0_26 no PIO1_8 no I/O PIO0_27 10 ns PIO0_31 no PIO0_30 no PIO1_6 no I/O PIO0_8 10 ns ...
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... NXP Semiconductors Table 3. Function RI 16-bit counter/timer CT16B0 CT16B0_CAP0 I CT16B0_CAP1 I CT16B0_CAP2 I CT16B0_MAT0 O CT16B0_MAT1 O CT16B0_MAT2 O 16-bit counter/timer CT16B1 CT16B1_CAP0 I CT16B1_CAP1 I CT16B1_CAP2 I CT16B1_MAT0 O CT16B1_MAT1 O CT16B1_MAT2 O LPC11AXX Product data sheet Pin multiplexing Type Port Glitch filter Pin I PIO0_30 no PIO0_31 no PIO1_3 no PIO0_2 50 ns PIO0_18 no PIO0_30 no PIO0_16 ...
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... NXP Semiconductors Table 3. Function 32-bit counter/timer CT32B0 CT32B0_CAP0 I CT32B0_CAP1 I CT32B0_CAP2 I CT32B0_MAT0 O CT32B0_MAT1 O CT32B0_MAT2 O CT32B0_MAT3 O 32-bit counter/timer CT32B1 CT32B1_CAP0 I CT32B1_CAP1 I CT32B1_CAP2 I CT32B1_MAT0 O CT32B1_MAT1 O CT32B1_MAT2 O CT32B1_MAT3 O Supply and ground pins V DD(IO) LPC11AXX Product data sheet Pin multiplexing Type Port Glitch filter Pin PIO0_11 10 ns ...
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... NXP Semiconductors Table 3. Function V DD(3V3 SS(IO) [1] Always on. [2] Programmable on/off. By default, the glitch filter is disabled. Table 4 listed first. All port pins PIO0_0 to PIO1_9 have internal pull-up resistors enabled after reset with the exception of the true open-drain pins PIO0_2 and PIO0_3. ...
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... NXP Semiconductors Table 4. LPC11Axx pin description table Symbol Pin/Ball PIO0_3/SDA/ACMP_O SWDIO/CT16B1_CAP0 PIO0_4/R/AOUT CT16B0_MAT1/MOSI0 TCK/SWCLK/PIO0_5 R/CT16B0_MAT2/ SCK0 TCK/SWCLK/PIO0_5 VDDCMP/ CT16B0_MAT2/ SCK0 LPC11AXX Product data sheet Type Reset Description state [1] [4][ PIO0_3 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 4. LPC11Axx pin description table Symbol Pin/Ball TDI/PIO0_6/AD0 CT32B0_MAT3/MISO0 TMS/PIO0_7/AD1 CT32B1_CAP0/ CT16B0_MAT0 TDO/PIO0_8/AD2 CT32B1_MAT0/SCK1 TRST/PIO0_9/AD3 CT32B1_MAT1/ CT16B0_MAT1/CTS LPC11AXX Product data sheet Type Reset Description state [1] [ TDI — Test Data In for JTAG interface. Input glitch filter (10 ns) capable ...
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... NXP Semiconductors Table 4. LPC11Axx pin description table Symbol Pin/Ball SWDIO/PIO0_10/AD4 CT32B1_MAT2/ CT16B0_MAT2/RTS PIO0_11/SCLK AD5/CT32B1_MAT3/ CT32B0_CAP0 PIO0_12/RXD ACMP_O/ CT32B0_MAT0/SCL/ CLKIN PIO0_13/TXD ACMP_I2/ CT32B0_MAT1/SDA LPC11AXX Product data sheet Type Reset Description state [1] [9] I SWDIO — Primary (default) Serial Wire Debug I/O for the LQFP48 and HVQFN33 packages ...
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... NXP Semiconductors Table 4. LPC11Axx pin description table Symbol Pin/Ball PIO0_14/MISO1/AD6 CT32B0_CAP1/ CT16B1_MAT1/ VDDCMP PIO0_14/MISO1/AD6 CT32B0_CAP1/ CT16B1_MAT1 PIO0_15/TXD/AD7 CT32B0_CAP2/SDA PIO0_16 ATRG0/ACMP_I3/ CT16B0_CAP1/SCL LPC11AXX Product data sheet Type Reset Description state [1] [7] I PIO0_14 — General purpose digital input/output pin. Input glitch filter (10 ns) capable ...
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... NXP Semiconductors Table 4. LPC11Axx pin description table Symbol Pin/Ball PIO0_17 ATRG1/ACMP_I4/ CT16B0_CAP2/ CT16B0_MAT0 PIO0_18/R/SSEL0 CT16B0_CAP0/ CT16B1_CAP1 PIO0_19/CLKIN CLKOUT/ MOSI0/CT16B1_MAT0 PIO0_20/R/SCK0 CT32B1_CAP0/ CT16B1_MAT2 PIO0_21/CTS ACMP_O/ CT32B1_CAP1/SCLK PIO0_22/MISO0 ACMP_I5/ CT32B1_MAT2/ CT32B1_CAP2 LPC11AXX Product data sheet ...
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... NXP Semiconductors Table 4. LPC11Axx pin description table Symbol Pin/Ball PIO0_23/RTS ACMP_O/ CT32B0_CAP0/SCLK PIO0_24/SCL/CLKIN CT16B1_CAP0 PIO0_25/SDA/SSEL1 CT16B1_MAT0 PIO0_26/TXD/MISO1 CT16B1_CAP1/ CT32B0_CAP2 PIO0_27/MOSI1 ACMP_I1/ CT32B1_MAT1/ CT16B1_CAP2 PIO0_28/DTR/SSEL1 CT32B0_CAP0 PIO0_29/DSR/SCK1 CT32B0_CAP1 LPC11AXX Product data sheet Type Reset Description state [1] [3] I/O I ...
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... NXP Semiconductors Table 4. LPC11Axx pin description table Symbol Pin/Ball PIO0_30/RI/MOSI1 CT32B0_MAT0/ CT16B0_CAP0 PIO0_31/RI/MOSI1 CT32B1_MAT0/ CT16B1_CAP1 PIO1_0/DCD/SCK0 CT32B1_MAT3/ CT16B0_MAT1 PIO1_1/DTR/SSEL0 CT32B1_MAT3/ CT16B1_MAT0 PIO1_2/DSR/MISO0 CT16B1_MAT2/ CT16B1_MAT1 PIO1_3/RI/MOSI0 CT16B1_CAP0 PIO1_4/RXD/SSEL1 CT32B0_MAT1/ CT32B1_CAP0/ CT16B0_CAP1 LPC11AXX Product data sheet Type Reset Description state ...
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... NXP Semiconductors Table 4. LPC11Axx pin description table Symbol Pin/Ball PIO1_5/TXD/SCK1 CT32B0_MAT2/ CT32B1_CAP1/ CT16B0_CAP2 PIO1_6/RTS/MOSI1 CT32B0_MAT3/ CT32B1_CAP2/ CT16B0_MAT0 PIO1_7/CTS/MOSI0 CT32B1_MAT1/ CT16B0_MAT2/ CT16B1_CAP2 PIO1_8/RXD / MISO1 CT32B1_MAT0/ CT16B1_MAT1 PIO1_9/DCD/ CT32B1_MAT2 / CT16B1_MAT2 XTALIN 6 4 XTALOUT DD(IO) LPC11AXX Product data sheet Type Reset Description state ...
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... NXP Semiconductors Table 4. LPC11Axx pin description table Symbol Pin/Ball SS(IO DD(3V3 [1] Pin state at reset for default function Input Output internal pull-up resistor (weak PMOS device) enabled inactive, no pull-up/down enabled. [2] See Figure 32 for the reset configuration. ...
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... NXP Semiconductors 7. Functional description 7.1 ARM Cortex-M0 processor The ARM Cortex- general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 On-chip flash program memory The LPC11Axx contain on-chip flash program memory. 7.3 On-chip EEPROM data memory The LPC11Axx contain on-chip EEPROM data memory ...
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... NXP Semiconductors LPC11Axx 4 GB reserved private peripheral bus reserved GPIO reserved APB peripherals 1 GB reserved 0.5 GB reserved 16 kB boot ROM reserved 8 kB SRAM (LPC11A1x/301, LPC11A04 SRAM (LPC11A1x/201 SRAM (LPC11Ax/101, LPC11A02 SRAM (LPC11Ax/001 on-chip flash (LPC11A14, LPC11A04 on-chip flash (LPC11A13) ...
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... NXP Semiconductors • Four programmable interrupt priority levels with hardware priority level masking. • Software interrupt generation. 7.7.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source ...
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... NXP Semiconductors • Control of the digital output slew rate allowing to switch more outputs simultaneously without degrading the power/ground distribution of the device. 7.10 USART The LPC11Axx contains one USART. Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. ...
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... NXP Semiconductors 2 The I C-bus is bidirectional for inter-IC control using only two wires: a serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed ...
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... NXP Semiconductors AD[7:0] ATRG[1:0] TEMPERATURE SENSOR 0.9 V VOLTAGE REFERENCE VDD(3V3) VOLTAGE VDDCMP DIVIDER REF ACMP_I[5:1] SIGNAL LEGEND: Fig 6. Configurable analog/mixed signal subsystem 7.14 10-bit ADC The LPC11Axx contains one ADC single 10-bit successive approximation ADC with eight channels. LPC11AXX Product data sheet CONFIGURABLE ANALOG/MIXED-SIGNAL SUBSYSTEM ...
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... NXP Semiconductors Fig 7. 7.14.1 Features • 10-bit successive approximation ADC. • Input multiplexing among 8 pins. • Power-down mode. • Measurement range 10-bit conversion time 2.44 s (up to 400 kSamples/s). • • Burst conversion mode for single or multiple inputs. • Optional conversion on transition of input pins ATRG0 or ATRG1, timer match signal, or comparator output ...
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... NXP Semiconductors • When the supply voltage V can be used to reduce the offset error E correction then increases the accuracy of temperature sensor voltage output measurements. • When the ADC is accurately calibrated, the internal voltage reference can be used to measure the power supply voltage. This requires calibration by recording the ADC code of the internal voltage reference at different power supply levels yielding a different ADC code value for each supply voltage level ...
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... NXP Semiconductors Fig 8. 7.17.1 Features • 10-bit DAC. • Resistor string architecture. • Buffered output. • Power-down mode. • Conversion speed controlled via a programmable bias current. • Optional output update modes: – write operations to the DAC register. – a transition of pins ATRG0 or ATRG1. Input signals must be held for a minimum of three system clock periods. – ...
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... NXP Semiconductors COMPARATOR ANALOG BLOCK V DD VDDCMP 32 internal voltage reference temperature sensor 5 ACMPI[5:1] Fig 9. Comparator block diagram 7.18.1 Features • Selectable 0 mV ( 5 mV), and 20 mV ( ( 20 mV) input hysteresis. • Five selectable external voltages; fully configurable on either positive or negative input channel. • ...
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... NXP Semiconductors 7.19 General purpose external event counter/timers The LPC11Axx includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt ...
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... NXP Semiconductors • Flag to indicate watchdog reset. • Programmable 24-bit timer with internal prescaler. • Selectable time period from (T multiples of T • The Watchdog Clock (WDCLK) source can be selected from the internal RC oscillator (IRC), or the dedicated watchdog oscillator (WDOsc). This gives a wide range of potential timing choices of watchdog operation under different power conditions ...
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... NXP Semiconductors IRC LFOsc MAINCLKSEL (main clock select) IRC SysOsc SYSTEM PLL CLKIN SYSPLLCLKSEL (system PLL clock select) Fig 10. LPC11Axx clock generation block diagram 7.22.1.1 Internal RC Oscillator (IRC) The IRC may be used as the clock source for the WWDT, and/or as the clock that drives the PLL and subsequently the CPU ...
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... NXP Semiconductors 7.22.1.3 Internal Low-Frequency Oscillator (LFOsc) and Watchdog Oscillator (WDOsc) The LFOsc and the WDOsc are identical internal oscillators. The nominal frequency is programmable between 9.4 kHz and 2.3 MHz. The frequency spread over silicon process variations is 40%. The WDOsc is a dedicated oscillator for the windowed WWDT. ...
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... NXP Semiconductors In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses ...
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... NXP Semiconductors 7.23.3 Brown-out detection The LPC11Axx include two programmable levels for monitoring the voltage on the V DD(3V3) signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; alternatively, software can monitor the signal by reading a dedicated status register. In addition, the BOD circuit supports one hardware controlled voltage level for triggering a chip reset ...
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... NXP Semiconductors 7.23.7 External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs. 7.24 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. JTAG and Serial Wire Debug (SWD) with four breakpoints and two watchpoints are supported. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH) ...
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... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V input/output supply voltage DD(IO) V input voltage I V analog input voltage IA V crystal input voltage i(xtal) I supply current DD ground current I/O latch-up current ...
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... NXP Semiconductors [4] Including the voltage on outputs in 3-state mode. [5] V present or not present. Compliant with the I DD(IO) [6] Applies tolerant pins PIO0_4 and PIO0_14 (LQFP and HVQFN packages) or PIO0_5 (WLCSP package). [7] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated exposure to elevated voltages at 4 ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V supply voltage (3.3 V) DD(3V3) V input/output supply DD(IO) voltage I supply current DD Standard port pins, RESET I LOW-level input current HIGH-level input IH current I OFF-state output OZ current ...
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... NXP Semiconductors Table 6. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V HIGH-level output OH voltage V LOW-level output OL voltage I HIGH-level output OH current I LOW-level output OL current I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current I pull-down current ...
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... NXP Semiconductors Table 6. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current C-bus pins (PIO0_2 and PIO0_3) V HIGH-level input IH voltage ...
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... NXP Semiconductors 9.1 Power consumption Power measurements in Active and Sleep modes were performed under the following conditions (see LPC11Axx user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. • Configure GPIO pins as outputs using the GPIOnDIR registers. ...
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... NXP Semiconductors (1) SysOsc and system PLL disabled; IRC enabled. (2) SysOsc and system PLL enabled; IRC disabled. Fig 12. Active mode: Typical supply current I (1) SysOsc and system PLL disabled; IRC enabled. (2) SysOsc and system PLL enabled; IRC disabled. Fig 13. Sleep mode: Typical supply current I ...
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... NXP Semiconductors 9.2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at T Table 7 ...
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... NXP Semiconductors (mA) Fig 15. High-current sink pins: Typical LOW-level output current I (mA) Fig 16. Typical LOW-level output current I LPC11AXX Product data sheet 0.2 Conditions 3 pins PIO0_2 and PIO0_3. DD(IO) output voltage 0.2 Conditions 3.3 V; standard port pins and PIO0_21. ...
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... NXP Semiconductors V Fig 17. Typical HIGH-level output voltage V (μA) Fig 18. Typical pull-up current I LPC11AXX Product data sheet 3 °C 25 °C 3.2 −40 °C 2.8 2 Conditions 3.3 V; standard port pins. DD(IO −10 − °C 25 °C −40 °C −50 − Conditions 3.3 V ...
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... NXP Semiconductors (μA) Fig 19. Typical pull-down current I LPC11AXX Product data sheet ° °C −40 ° Conditions 3.3 V; standard port pins. DD(IO) pd All information provided in this document is subject to legal disclaimers. Rev. 4 — 30 October 2012 LPC11Axx 32-bit ARM Cortex-M0 microcontroller ...
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... NXP Semiconductors 10. Dynamic characteristics 10.1 Power supply fluctuations If the input voltage (V reset during a brown-out condition as long as the UVLO circuit is operating. The settling times of the BOD and POR circuits, which constitute the UVLO, determine the minimum time the supply level must remain in the shallow or deep brown-out condition to ensure that the internal reset is asserted properly ...
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... NXP Semiconductors Table 9. amb specified below. Symbol t ret prog [1] Number of program/erase cycles. [2] Min and max values are valid for T [3] Programming times are given for writing 256 bytes to the flash. T flash in blocks of 256 bytes. Flash programming is accomplished via IAP calls (see LPC11Axx user manual) ...
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... NXP Semiconductors Fig 21. External clock timing (with an amplitude of at least V 10.4 Internal oscillators Table 12. amb Symbol f osc(RC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages ...
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... NXP Semiconductors [2] The typical frequency spread over processing and temperature (T [3] See the LPC11Axx user manual. 10.5 I/O pins Table 14. amb Symbol [1] Applies to standard port pins and RESET pin. Simulated results. [2] SSO indicates maximum number of simultaneously switching digital output pins. The pins are optimized for half of the maximum SSO ...
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... NXP Semiconductors Table 15. amb Symbol t HIGH t HD;DAT t SU;DAT [1] See the I [2] Parameters are valid over operating temperature range unless otherwise specified. [3] t HD;DAT and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V (min) of the SCL signal) to bridge the undefined region of the falling edge of SCL ...
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... NXP Semiconductors SDA SCL SCL 2 Fig 23. I C-bus pins clock timing 10.7 SSP interfaces Table 16. Dynamic characteristics of SSP pins in SPI mode 2.6 V < <= 3.6 V. DD(3V3) DD(IO) Symbol Parameter SPI master (in SPI mode) T clock cycle time cy(clk) t data set-up time ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 24. SSP master timing in SPI mode LPC11AXX Product data sheet T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID MOSI DATA VALID MISO Pin names SCK, MISO, and MOSI refer to pins for both SSP peripherals, SSP0 and SSP1. ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 25. SSP slave timing in SPI mode 11. Characteristics of analog peripherals Table 17 amb Symbol V th [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC11Axx user manual. LPC11AXX Product data sheet ...
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... NXP Semiconductors Table 18. amb 3 Symbol L(adj err(FS [1] The ADC is monotonic, there are no missing codes. [2] The differential linearity error (E See [3] The integral non-linearity (E the ideal transfer curve after appropriate adjustment of gain and offset errors. See ...
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... NXP Semiconductors Table 19. V DD(3V3) Symbol L(adj c(DAC [1] Measured on typical samples. Table 20. Bias bit 0 1 LPC11AXX Product data sheet DAC static and dynamic characteristics +85 amb Parameter Conditions ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors Table 21. Symbol s(pu) t s(sw) [1] Characterized through simulation. [2] Characterized on a typical silicon sample. [3] Typical values are derived from nominal simulation (V models). Maximum values are derived from worst case simulation (V process models). [4] Settling time applies to switching between comparator and ADC channels. ...
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... NXP Semiconductors Table 22. V DD(3V3) Symbol DT sen s(pu) t s(sw) [1] Absolute temperature accuracy. [2] Typical values are derived from nominal simulation (V models). Maximum values are derived from worst case simulation (V process models). [3] Settling time applies to switching between comparator and ADC channels. Table 23. ...
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... NXP Semiconductors Table 24. Comparator characteristics 3.0 V and unless noted otherwise. DD(3V3) amb Symbol Parameter Static characteristics I supply current DD V common-mode input voltage IC DV output voltage variation O V offset voltage offset Dynamic characteristics t start-up time startup t propagation delay PD t propagation delay ...
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... NXP Semiconductors Table 25. Symbol t s(pu) t s(sw) [1] Maximum values are derived from worst case simulation (V models). [2] Settling time applies to switching between comparator and ADC channels. Table 26. V DD(3V3) Symbol E V(O) E V(O) Measured over a polyresistor matrix lot with a 2 kHz input signal and overdrive < 100 V. ...
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... NXP Semiconductors 12. Application information 12.1 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in • The ADC input trace must be short and as close as possible to the LPC11Axx chip. • The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines. • ...
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... NXP Semiconductors R ). Capacitance C S not be larger than 7 pF. Parameters F manufacturer (see Fig 30. Oscillator modes and models: oscillation mode of operation and external crystal Table 27. Fundamental oscillation frequency F 1 MHz - 5 MHz 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 28. Fundamental oscillation frequency F 15 MHz - 20 MHz ...
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... NXP Semiconductors 12.4 XTAL Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain ...
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... NXP Semiconductors 12.6 Reset pad configuration Fig 32. Reset pad configuration 12.7 UVLO protection and reset timer circuit V EXT 3 POR Fig 33. Functional diagram of the UVLO protection and reset timer circuit 12.8 Guidelines for selecting a power supply filter for UVLO protection For the UVLO circuits to hold the part in reset during shallow and deep brown-out ...
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... NXP Semiconductors = 5 s for shallow brown-out (see • s for deep brown-out (see • With these parameters, the decoupling/bypass capacitor to add to the supply line is: C 0.15 F for shallow brown-out • C >> 0.36 F for deep brown-out • LPC11AXX ...
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... NXP Semiconductors 13. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (1) Unit max 1.00 0.05 0.35 mm nom 0.85 0.02 0.28 0.2 min 0.80 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (mm are the original dimensions) (1) (1) Unit max 0.05 0.30 mm nom 0.85 0.2 min 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors WLCSP20: wafer level chip-size package; 20 bumps; 2.5 x 2.5 x 0.6 mm ball A1 index area ball A1 1 index area Dimensions (mm are the original dimensions) Unit max 0.65 0.27 0.38 0.35 2.60 2.60 mm nom 0.60 0.24 0.36 0.32 2.55 2.55 min 0.55 0.21 0.34 0.29 2.50 2.50 Outline version IEC LPC11AxxUK Fig 37. Package outline (WLCSP20) LPC11AXX Product data sheet ...
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... NXP Semiconductors 14. Soldering Footprint information for reflow soldering of LQFP48 package solder land occupied area DIMENSIONS 0.500 0.560 10.350 10.350 7.350 Fig 38. Reflow soldering of the LQFP48 package LPC11AXX Product data sheet (8× Generic footprint pattern ...
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... NXP Semiconductors Footprint information for reflow soldering of HVQFN33 package solder land solder paste deposit occupied area Fig 39. Reflow soldering of the HVQFN33(7x7) package LPC11AXX Product data sheet OID = 8.20 OA PID = 7.25 PA+OA OwDtot = 5.10 OA evia = 4.25 0.20 SR chamfer (4×) SPD = 1.00 SP GapD = 0.70 SP evia = 2.40 SDhtot = 2.70 SP 4.55 SR DHS = 4.85 CU LbD = 5.80 CU LaD = 7.95 CU solder land plus solder paste ...
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... NXP Semiconductors Footprint information for reflow soldering of HVQFN33 package see detail X Hy solder land solder paste occupied area Dimensions 0.5 5.95 5.95 4.25 4.25 11-11-15 Issue date 11-11-20 Fig 40. Reflow soldering of the HVQFN33(5x5) package LPC11AXX Product data sheet Hx Gx nSPx Gy SLy C SLx ...
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... NXP Semiconductors 15. Abbreviations Table 29. Acronym ADC AHB AMBA APB BOD GPIO I2C JEDEC LVTSCR NVM PLL SPI SSI TTL USART UVLO LPC11AXX Product data sheet Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Brown-Out Detection ...
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... NXP Semiconductors 16. Revision history Table 30. Revision history Document ID Release date LPC11AXX v.4 20121030 LPC11AXX v.3 20120907 LPC11AXX v.2.1 20120704 LPC11AXX Product data sheet Data sheet status Product data sheet • Parameter t corrected in Table PD • Editorial updates. • Maximum and minimum values for V values”. ...
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... NXP Semiconductors Table 30. Revision history …continued Document ID Release date LPC11AXX v.2 20120625 LPC11AXX v.1 20120322 LPC11AXX Product data sheet Data sheet status Preliminary data sheet - • Data sheet status changed to Preliminary. • Parameter f removed from Table 11. clk • t removed in Table 11. er • Writable EEPROM size specified in Section 7.3. ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . 23 7.1 ARM Cortex-M0 processor . . . . . . . . . . . . . . . 23 7.2 On-chip flash program memory . . . . . . . . . . . 23 7.3 On-chip EEPROM data memory 7.4 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 23 7 ...
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... NXP Semiconductors 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 78 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 79 17 Legal information 17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 81 17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 17.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 32-bit ARM Cortex-M0 microcontroller Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. ...