LPC11A14FBD48/301, NXP Semiconductors, LPC11A14FBD48/301, Datasheet - Page 26

• Manufacturer Part Number: LPC11A14FBD48/301,
• Description: ARM Microcontrollers - MCU CortexM0 32bit 32KB
• Manufacturer: NXP Semiconductors

Specifications of LPC11A14FBD48/301,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11A
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.6 V to 3.6 V
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 250

NXP Semiconductors
LPC11AXX
Product data sheet
7.10.1 Features
7.11.1 Features
7.10 USART
7.12 I
7.11 SSP serial I/O controller
The LPC11Axx contains one USART.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The USART includes a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
The LPC11Axx contain two SSP controllers.
The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. The SSP supports full
duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
The LPC11Axx contains one I
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C-bus serial I/O controller
Control of the digital output slew rate allowing to switch more outputs simultaneously
without degrading the power/ground distribution of the device.
Maximum USART data bit rate of 3.125 MBit/s.
16-byte Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
FIFO control mechanism that enables software flow control implementation.
Support for RS-485/9-bit mode.
Supports a full modem control handshake interface.
Support for synchronous mode.
Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SPI mode)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
2
C-bus controller.
32-bit ARM Cortex-M0 microcontroller
LPC11Axx
© NXP B.V. 2012. All rights reserved.
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