LPC11A14FBD48/301, NXP Semiconductors, LPC11A14FBD48/301, Datasheet - Page 27

• Manufacturer Part Number: LPC11A14FBD48/301,
• Description: ARM Microcontrollers - MCU CortexM0 32bit 32KB
• Manufacturer: NXP Semiconductors

Specifications of LPC11A14FBD48/301,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11A
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.6 V to 3.6 V
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 250

NXP Semiconductors
LPC11AXX
Product data sheet
7.12.1 Features
7.13 Configurable analog/mixed-signal subsystems
The I
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
Remark: On the WLCSP package, the bootloader configures the open-drain pins
(PIO0_2 and PIO0_3) for the Serial Wire Debug (SWD) function.
Multiple analog/mixed-signal subsystems can be configured by software from
interconnected digital and analog peripherals. See
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The I
(PIO0_2 and PIO0_3). The I
rates up to 1 Mbit/s. For the I
The true open-drain pins PIO0_2 and PIO0_3 can be configured with a 50 ns digital
input glitch filter.
If the true open-drain pins are used for other purposes, a limited-performance I
interface can be configured from a choice of six GPIO pins configured in open-drain
mode and with a pull-up resistor. In this mode, typical bit rates of up to 100 kbit/s with
20 pF load are supported if the internal pull-ups are enabled. Higher bit rates can be
achieved with an external resistor.
Fail-safe operation: When the power to an I
and SCL pins connected to the I
Easy to configure as master, slave, or master/slave.
ROM-based I
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
The I
2
C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
2
2
2
C-interface is a standard I
C-bus can be used for test and diagnostic purposes.
C-bus controller supports multiple address recognition and a bus monitor mode.
All information provided in this document is subject to legal disclaimers.
2
C-bus driver routines to easily create applications.
Rev. 4 — 30 October 2012
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2
C-bus interface also supports Fast-mode Plus with bit
C-bus specification, see UM10204.
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2
C-bus compliant interface with open-drain pins
C-bus are floating and do not disturb the bus.
2
C-bus device is switched off, the SDA
32-bit ARM Cortex-M0 microcontroller
Figure
2
C is a multi-master bus and can be
6.
LPC11Axx
© NXP B.V. 2012. All rights reserved.
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C-bus