LPC11A14FBD48/301, NXP Semiconductors, LPC11A14FBD48/301, Datasheet - Page 22

• Manufacturer Part Number: LPC11A14FBD48/301,
• Description: ARM Microcontrollers - MCU CortexM0 32bit 32KB
• Manufacturer: NXP Semiconductors

Specifications of LPC11A14FBD48/301,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11A
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.6 V to 3.6 V
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 250

NXP Semiconductors
Table 4.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] I
[11] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
[12] If separate supplies are used for V
[13] If separate supplies are used for V
[14] Thermal pad (HVQFN33 pin package). Connect to ground.
LPC11AXX
Product data sheet
Symbol
V
V
V
SS(IO)
DD(3V3)
SS
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up resistor (weak PMOS device) enabled; IA = inactive, no
pull-up/down enabled.
See
5 V tolerant pin providing standard digital I/O functions with configurable modes and configurable hysteresis
I
For the SWD function, a pull-up resistor is recommended for the SWCLK pin (WLCSP20 parts only).
For the SWD function, a pull-up resistor is recommended for the SWDIO pin (WLCSP20 parts only).
Not a 5 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with configurable modes,
configurable hysteresis, and analog I/O. When configured as an analog I/O, the digital section of the pin is disabled
If this pin is configured for its VDDCMP function, it cannot be used for SWCLK when the part is on the board. The bypass filter of the
power supply filters out the SWCLK clock input signal.
5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O. When
configured as an analog I/O, digital section of the pin is disabled, and the pin is not 5 V tolerant
specification. Pins can be configured with an on-chip pull-up resistor (pMOS device) and with open-drain mode. In this mode, typical bit
rates of up to 100 kbit/s with 20 pF load are supported if the internal pull-ups are enabled. Higher bit rates can be achieved with an
external resistor.
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. See
connected to the XTALIN pin.
corresponding grounds V
also
to 0.5 V.
2
2
C-bus pins compliant with the I
C-bus pins are standard digital I/O pins and have limited performance and electrical characteristics compared to the full I
Figure 32
Section
LPC11Axx pin description table
12.1).
for the reset configuration.
Pin/Ball
5
44 29 E2
42 33 E3
SS
and V
33 E3
2
C-bus specification for I
SS(IO)
DD(3V3)
DD(3V3)
(LQFP48 package). Using separate filtered supplies reduces the noise to the analog blocks (see
[14]
[12]
[13]
[14]
and V
and V
All information provided in this document is subject to legal disclaimers.
Type Reset
-
-
-
DD(IO)
DD(IO)
Rev. 4 — 30 October 2012
, ensure that the voltage difference between both supplies is smaller than or equal
, ensure that the power supply pins are filtered for noise with respect to their
state
[1]
-
-
-
2
C standard mode, I
Description
Ground.
3.3 V supply voltage to the analog blocks, internal regulator,
and internal clock generator circuits. Also used as the ADC
reference voltage.
Ground.
2
C Fast-mode, and I
32-bit ARM Cortex-M0 microcontroller
Section 12.3
(Figure
2
C Fast-mode Plus.
31).
LPC11Axx
(Figure
if an external clock is
© NXP B.V. 2012. All rights reserved.
(Figure
31).
2
C-bus
31).
22 of 84