LPC11A14FBD48/301, NXP Semiconductors, LPC11A14FBD48/301, Datasheet - Page 37

• Manufacturer Part Number: LPC11A14FBD48/301,
• Description: ARM Microcontrollers - MCU CortexM0 32bit 32KB
• Manufacturer: NXP Semiconductors

Specifications of LPC11A14FBD48/301,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11A
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.6 V to 3.6 V
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 250

NXP Semiconductors
LPC11AXX
Product data sheet
7.22.6.2 Power profiles
7.23.1 UnderVoltage LockOut (UVLO) protection
7.23.2 Reset
7.23 System control
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC11Axx for one of the following power modes:
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
The BOD and POR circuits remain enabled at all times to provide UVLO protection from
an unexpected power supply droop below a typical threshold level of 2.4 V (see also the
LPC11Axx user manual). UVLO protection means that the LPC11Axx is held in reset
whenever the supply voltage falls below 2.4 V.
See also
reset timer
UVLO
Reset has several sources on the LPC11Axx: the RESET pin, the Watchdog reset,
power-on reset (POR), the ARM SYSRESETREQ software request, and the Brown-Out
Detection (BOD) circuit. After the BOD and the POR resets are released, the internal reset
timer counts for 100 μs until the internal reset is removed.
Assertion of chip reset by any source (after the operating voltage attains a usable level)
starts the IRC and initializes the flash memory controller.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Writing to a special function register allows the software to reset the following peripherals:
the I
comparator, the ADC, and the DAC.
The RESET pin is a Schmitt trigger input pin and uses a special pad. See
•
•
•
•
Default mode corresponding to power configuration after reset.
CPU performance mode corresponding to optimized processing capability.
Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
Low-current mode corresponding to lowest power consumption.
2
C-bus interface, the USART, both SSP controllers, the four counter/timers, the
protection”.
Section 10.1 “Power supply
circuit”, and
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
Section 12.8 “Guidelines for selecting a power supply filter for
fluctuations”,
32-bit ARM Cortex-M0 microcontroller
Section 12.7 “UVLO protection and
LPC11Axx
© NXP B.V. 2012. All rights reserved.
Figure
32.
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