LPC11A14FBD48/301, NXP Semiconductors, LPC11A14FBD48/301, Datasheet - Page 36

• Manufacturer Part Number: LPC11A14FBD48/301,
• Description: ARM Microcontrollers - MCU CortexM0 32bit 32KB
• Manufacturer: NXP Semiconductors

Specifications of LPC11A14FBD48/301,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11A
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.6 V to 3.6 V
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 250

NXP Semiconductors
LPC11AXX
Product data sheet
7.22.1.3 Internal Low-Frequency Oscillator (LFOsc) and Watchdog Oscillator (WDOsc)
7.22.6.1 Sleep mode
7.22.2 Clock input
7.22.3 System PLL
7.22.4 Clock output
7.22.5 Wake-up process
7.22.6 Power control
The LFOsc and the WDOsc are identical internal oscillators. The nominal frequency is
programmable between 9.4 kHz and 2.3 MHz. The frequency spread over silicon process
variations is  40%.
The WDOsc is a dedicated oscillator for the windowed WWDT.
The LFOsc can be used as a clock source that directly drives the CPU or the CLKOUT
pin.
A 3.3 V external clock source (25 MHz typical) can be supplied on the selected CLKIN pin
or a 1.8 V external clock source can be supplied on the XTALIN pin (see
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The output
divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the
minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.
The PLL is turned off and bypassed following a chip reset and may be enabled by
software. The program must configure and activate the PLL, wait for the PLL to lock, and
then connect to the PLL as a clock source. The PLL settling time is 100 s.
The LPC11Axx features a clock output function that routes the IRC, the SysOsc, the
LFOsc, or the main clock to an output pin.
The LPC11Axx begin operation at power-up by using the IRC as the clock source. This
allows chip operation to resume quickly. If the SysOsc, the external clock source, or the
PLL is needed by the application, software will need to enable these features and wait for
them to stabilize before they are used as a clock source.
The LPC11Axx supports the ARM Cortex-M0 Sleep mode. The CPU clock rate may also
be controlled as needed by changing clock sources, reconfiguring PLL values, and/or
altering the CPU clock divider value. This allows a trade-off of power versus processing
speed based on application requirements. In addition, a register is provided for shutting
down the clocks to individual on-chip peripherals, allowing fine tuning of power
consumption by eliminating all dynamic power use in any peripherals that are not required
for the application. Selected peripherals have their own clock divider which provides even
better power control.
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
32-bit ARM Cortex-M0 microcontroller
LPC11Axx
© NXP B.V. 2012. All rights reserved.
Section
12.3).
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