LPC11A14FBD48/301, NXP Semiconductors, LPC11A14FBD48/301, Datasheet - Page 13

• Manufacturer Part Number: LPC11A14FBD48/301,
• Description: ARM Microcontrollers - MCU CortexM0 32bit 32KB
• Manufacturer: NXP Semiconductors

Specifications of LPC11A14FBD48/301,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11A
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.6 V to 3.6 V
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 250

NXP Semiconductors
Table 4.
LPC11AXX
Product data sheet
Symbol
RESET/PIO0_0
PIO0_1/RXD/CLKOUT/
CT32B0_MAT2/SSEL0/
CLKIN
PIO0_2/SCL/ACMP_O/
TCK/SWCLK/
CT16B0_CAP0
LPC11Axx pin description table
Table 3.
[1]
[2]
Table 4
listed first. All port pins PIO0_0 to PIO1_9 have internal pull-up resistors enabled after
reset with the exception of the true open-drain pins PIO0_2 and PIO0_3.
Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed
through the IOCON registers for each of the port pins.
Function
V
V
V
Pin/Ball
3
4
15 10 A1
DD(3V3)
SS
SS(IO)
Always on.
Programmable on/off. By default, the glitch filter is disabled.
2
3
shows all pins in order of their port number. The default function after reset is
C1
B2
Pin multiplexing
[2]
[3]
[4][5]
All information provided in this document is subject to legal disclaimers.
Type
Supply
Ground
Ground
Type Reset
I
I/O
I/O
I
O
O
I/O
I
I/O
I/O
O
I
I
Rev. 4 — 30 October 2012
state
[1]
I; PU
-
I; PU
-
-
-
-
-
I; IA
-
-
-
-
Port
-
-
-
Description
RESET — External reset input with fixed 20 ns glitch filter: A
LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states and processor
execution to begin at address 0.
PIO0_0 — General purpose digital input/output pin.
PIO0_1 — General purpose digital input/output pin. A LOW
level on this pin during reset starts the ISP command handler.
RXD — Receiver data input for USART.
CLKOUT — Clock output.
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
SSEL0 — Slave Select for SSP0.
CLKIN — External clock input.
PIO0_2 — General purpose digital input/output pin.
High-current sink (20 mA) or standard-current sink (4 mA)
programmable; true open-drain for all pin functions. Input
glitch filter (50 ns) capable.
SCL — I
glitch filter (50 ns) capable.
ACMP_O — Analog comparator output.
TCK/SWCLK — Serial Wire Debug Clock (secondary for
LQFP and HVQFN packages). Input glitch filter (50 ns)
capable. For the WLCSP20 package only, this pin is
configured to the SWCLK function by the boot loader after
reset.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. Input
glitch filter (50 ns) capable.
Glitch filter Pin
-
-
-
2
C-bus clock (true open-drain) input/output. Input
32-bit ARM Cortex-M0 microcontroller
LQFP48
44
42
5
HVQFN33
Pin
29
33
33
LPC11Axx
© NXP B.V. 2012. All rights reserved.
WCSP20
Ball
E2
E3
E3
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