LPC11A14FBD48/301, NXP Semiconductors, LPC11A14FBD48/301, Datasheet - Page 2

• Manufacturer Part Number: LPC11A14FBD48/301,
• Description: ARM Microcontrollers - MCU CortexM0 32bit 32KB
• Manufacturer: NXP Semiconductors

Specifications of LPC11A14FBD48/301,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11A
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.6 V to 3.6 V
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 250

NXP Semiconductors
LPC11AXX
Product data sheet





Analog peripherals:
Serial interfaces:
Clock generation:
Power control:
Unique device serial number for identification.



























Up to 16 pins are configurable with a digital input glitch filter for removing glitches
with widths of 10 ns or less and two pins are configurable for 50 ns glitch filters.
GPIO pins can be used as edge and level sensitive interrupt sources.
High-current source output driver (20 mA) on one pin (PIO0_21).
High-current sink driver (20 mA) on true open-drain pins (PIO0_2 and PIO0_3).
Four general purpose counter/timers with a total of up to 16 capture inputs and 14
match outputs.
Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal
low-power WatchDog Oscillator (WDOsc).
10-bit ADC with input multiplexing among 8 pins.
10-bit DAC with flexible conversion triggering.
Highly flexible analog comparator with a programmable voltage reference.
Integrated temperature sensor.
Internal voltage reference.
UnderVoltage Lockout (UVLO) protection against power-supply droop below 2.4 V.
USART with fractional baud rate generation, internal FIFO, support for
RS-485/9-bit mode and synchronous mode.
Two SSP controllers with FIFO and multi-protocol capabilities. Support data rates
of up to 25 Mbit/s.
I
a data rate of 1 Mbit/s with multiple address recognition and monitor mode.
Crystal Oscillator (SysOsc) with an operating range of 1 MHz to 25 MHz.
12 MHz internal RC Oscillator (IRC) trimmed to 1% accuracy that can optionally be
used as a system clock.
Internal low-power, Low-Frequency Oscillator (LFOsc) with programmable
frequency output.
Clock input for external system clock (25 MHz typical).
PLL allows CPU operation up to the maximum CPU rate with the IRC, the external
clock, or the SysOsc as clock sources.
Clock output function with divider that can reflect the SysOsc, the IRC, the main
clock, or the LFOsc.
Supports one reduced power mode: The ARM Sleep mode.
Power profiles residing in boot ROM allowing to optimize performance and
minimize power consumption for any given application through one simple function
call.
Processor wake-up from reduced power mode using any interrupt.
Power-On Reset (POR).
Brown-Out Detect (BOD) with two programmable thresholds for interrupt and one
hardware controlled reset trip point.
POR and BOD are always enabled for rapid UVLO protection against power supply
voltage droop below 2.4 V.
2
C-bus interface supporting the full I
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
2
C-bus specification and Fast-mode Plus with
32-bit ARM Cortex-M0 microcontroller
LPC11Axx
© NXP B.V. 2012. All rights reserved.
2 of 84