LPC11A14FBD48/301, NXP Semiconductors, LPC11A14FBD48/301, Datasheet - Page 25

• Manufacturer Part Number: LPC11A14FBD48/301,
• Description: ARM Microcontrollers - MCU CortexM0 32bit 32KB
• Manufacturer: NXP Semiconductors

Specifications of LPC11A14FBD48/301,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11A
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.6 V to 3.6 V
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 250

NXP Semiconductors
LPC11AXX
Product data sheet
7.7.2 Interrupt sources
7.9.1 Features
7.8 IOCON block
7.9 Fast general purpose parallel I/O
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Up to eight GPIO pins, regardless of the selected function, can be programmed to
generate an interrupt on a level, or rising edge or falling edge, or both. The interrupt
generating GPIOs can be selected from the GPIO pins with a configurable input glitch
filter.
The IOCON block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Up to 16 pins can be configured with a digital input glitch filter for removing voltage
glitches with widths of 10 ns or less (see
PIO0_3) can be configured with a 50 ns digital input glitch filter.
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs
can be set or cleared in one write operation.
LPC11Axx use accelerated GPIO functions:
Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be
programmed to generate an interrupt on a level, a rising or falling edge, or both.
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Four programmable interrupt priority levels with hardware priority level masking.
Software interrupt generation.
GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved.
An entire port value can be written in one instruction.
Bit level port registers allow a single instruction to set and clear any number of bits in
one write operation.
Direction control of individual bits.
All I/O default to inputs with internal pull-up resistors enabled after reset - except for
the I
Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed
through the IOCON block for each GPIO pin (see
functional diagrams).
2
C-bus true open-drain pins PIO0_2 and PIO0_3.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
Table 3
32-bit ARM Cortex-M0 microcontroller
and
Table
Figure 31
4), two pins (PIO0_2 and
and
LPC11Axx
Figure 32
© NXP B.V. 2012. All rights reserved.
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