LPC11A14FBD48/301, NXP Semiconductors, LPC11A14FBD48/301, Datasheet - Page 23

• Manufacturer Part Number: LPC11A14FBD48/301,
• Description: ARM Microcontrollers - MCU CortexM0 32bit 32KB
• Manufacturer: NXP Semiconductors

Specifications of LPC11A14FBD48/301,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11A
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.6 V to 3.6 V
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 250

NXP Semiconductors
7. Functional description
LPC11AXX
Product data sheet
7.1 ARM Cortex-M0 processor
7.2 On-chip flash program memory
7.3 On-chip EEPROM data memory
7.4 On-chip SRAM
7.5 On-chip ROM
7.6 Memory map
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption.
The LPC11Axx contain up to 32 kB of on-chip flash program memory.
The LPC11Axx contain up to 4 kB of on-chip EEPROM data memory.
Remark: The top 64 bytes of the 4 kB EEPROM memory are reserved and cannot be
written to. The entire EEPROM is writable for smaller EEPROM sizes.
The LPC11Axx contain a total of 8 kB, 4 kB, or 2 kB on-chip static RAM data memory.
The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (API):
The LPC11Axx incorporates several distinct memory regions, shown in the following
figures.
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
•
•
•
•
In-System Programming (ISP) and In-Application Programming (IAP) support for flash
programming
Power profiles for configuring power consumption and PLL settings
32-bit integer division routines
I
2
C-bus driver routines
Figure 5
All information provided in this document is subject to legal disclaimers.
shows the overall map of the entire address space from the user
Rev. 4 — 30 October 2012
32-bit ARM Cortex-M0 microcontroller
LPC11Axx
© NXP B.V. 2012. All rights reserved.
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