OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 91

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Data Sheet
June 1999
Lucent Technologies Inc.
Configuration Data Format
The length and number of data frames and information on the PROM size for the Series 3 FPGAs are given in
Table 33.
Table 33. Configuration Frame Size
Bit Stream Error Checking
There are three different types of bit stream error checking performed in the ORCA Series 3 FPGAs:
ID frame, frame alignment, and CRC checking.
The ID data frame is sent to a dedicated location in the FPGA. This ID frame contains a unique code for the device
for which it was generated. This device code is compared to the internal code of the FPGA. Any differences are
flagged as an ID error. This frame is automatically created by the bit stream generation program in ORCA Foundry.
Each data and address frame in the FPGA begins with a frame start pair of bits and ends with eight stop bits set to
1. If any of the previous stop bits were a 0 when a frame start pair is encountered, it is flagged as a frame align-
ment error.
Error checking is also done on the FPGA for each frame by means of a checksum byte. If an error is found on eval-
uation of the checksum byte, then a checksum/parity error is flagged. The checksum is the XOR of all the data
bytes, from the start of frame up to and including the bytes before the checksum. It applies to the ID, address, and
data frames.
When any of the three possible errors occur, the FPGA is forced into an idle state, forcing INIT low. The FPGA will
remain in this state until either the
If using either of the MPI modes to configure the FPGA, the specific type of bit stream error is written to one of the
MPI registers by the FPGA configuration logic. The
out of the error condition and restart configuration.
Configuration Data (# of frames x # of data
Maximum Total # Bits/Frame (align bits, 01
Maximum Configuration Data (# bits/frame
(add configuration header and postamble)
frame start, 8-bit checksum, 8 stop bits)
Maximum PROM Size (bits)
Data Bits/Frame
x # of frames)
# of Frames
bits/frame)
Devices
RESET
(continued)
or
PRGM
OR3T20
172,912
191,744
191,912
856
202
224
pins are asserted.
PGRM
bit of the MPI control register can also be used to reset
OR3T30
228,288
251,904
252,072
984
232
256
OR3C/T55
ORCA Series 3C and 3T FPGAs
362,080
386,880
387,048
1240
292
312
OR3C/T80
526,592
562,496
562,664
1496
352
376
OR3T125
830,960
872,320
872,488
1880
442
464
91