OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 76

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
2x Clock Duty-Cycle Adjustment
A doubled-frequency, duty-cycle adjusted version of the
input clock can be constructed in DLL mode. The first
clock cycle of the 2x clock output occurs when the input
clock is high, and the second cycle occurs when the
input clock is low. The duty cycle can be adjusted in
1/32 (6.25%) increments of the input clock period.
Additionally, each of the two doubled-clock cycles that
occurs in a single input clock cycle may be adjusted to
have different duty cycles. DLL 2x clock mode is
selected by setting bit 4 of register five to a 1, and by
setting register six, bits [5:4] to 01 for ExpressCLK out-
put, and/or bits [7:6] to 01 for system clock output. The
duty-cycle percentage value is entered in register
three. See register three programming details for more
information. Duty-cycle values where both cycles of the
doubled clock have the same duty cycle are also shown
in Table 28.
Table 28 . DLL Mode Delay/2x Duty Cycle
Phase-Locked Loop (PLL) Mode
The PLL mode of the PCM is used for clock multiplica-
tion (1/8x to 64x) and clock delay minimization func-
tions. PLL functions make use of the PCM dividers and
use feedback signals, often from the FPGA array. The
use of feedback is discussed with each PLL submode.
PLL mode is selected by setting bit 0 of register five to
1.
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Register 3 [7:0]
Programming Values
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 1
0 0 0 1 0 0 1 0
0 0 0 1 1 0 1 1
0 0 1 0 0 1 0 0
0 0 1 0 1 1 0 1
0 0 1 1 0 1 1 0
0 0 1 1 1 1 1 1
1 1 0 0 0 0 0 0
1 1 0 0 1 0 0 1
1 1 0 1 0 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 0 1 0 0
1 1 1 0 1 1 0 1
1 1 1 1 0 1 1 0
Duty Cycle
12.50
18.75
25.00
31.25
37.50
43.75
50.00
56.25
62.50
68.75
75.00
81.25
87.50
93.75
(%)
6.25
Clock Delay Minimization
PLL mode can be used to minimize the effects of the
input buffer and input routing delay on the clock signal.
PLL mode causes a feedback clock signal to align in
phase with the input clock (refer back to the block dia-
gram in Figure 45) so that the delay between them is
effectively eliminated.
There is a dedicated feedback path from an adjacent
middle CLKCNTRL block to the PCM . Using the corner
ExpressCLK pad as the input to the PCM and using this
dedicated feedback path, the clock from the Express-
CLK output of the PCM , as viewed at the CLKCNTRL
block, will be phase-aligned with the ExpressCLK input
to the PCM . These relationships are diagrammed in
Figure 47.
A feedback clock can also be input to the PCM from
general routing. This allows for compensating for delay
between the PCM input and a point in the general rout-
ing. The use of this routed-feedback path is not gener-
ally recommended. Because compensation is based
on the programmable routing, the amount of clock
delay compensation can vary between FPGA lots and
fabrication processes, and will vary each time that the
feedback line is routed using different resources. Con-
tact Lucent Technologies for application notes regard-
ing the use of routed-feedback delay compensation.
Figure 47. ExpressCLK Delay Minimization
OUTPUT WITHOUT
EXPRESSCLK
EXPRESSCLK
EXPRESSCLK
USING PCM
CLKCNTRL
USING PCM
CORNER
CLKCNTRL
OUTPUT
INPUT
Using the PCM
COMPENSATION EQUALS DELAY
DELAY IS COMPENSATED
DELAY
Lucent Technologies Inc.
Data Sheet
June 1999
5-5980(F)