OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 116

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

ORCA Series 3C and 3T FPGAs
Timing Characteristics
Table 49. Microprocessor Interface (MP I) Timing Characteristics (continued)
OR3Cxx Commercial: V
OR3Txxx Commercial: V
10. User should set up read data so that RDS_SET and RDS_HLD can be met for the microprocessor timing.
Notes:
Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host ( PowerPC , i960 ) from the FPGA.
PowerPC and i960 timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK).
116
User Logic Delay
User Start Delay (MPI_CLK falling to USTART)
User Start Clear Delay (MPI_CLK to USTART)
User End Delay (USTART low to UEND low)
Synchronous User Timing:
Asynchronous User Timing:
1. For user system flexibility,
2. 0.5 MPI_CLK.
3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized.
4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV.
5. User Logic Delay has no predefined value. The user must generate a UEND signal to complete the cycle.
6. USTART_DEL is based on the falling clock edge.
7. There is no specific time associated with this delay. The user must assert UEND low to complete this cycle.
8. The user must assert interrupt request low until a service routine is executed.
9. This should be at least one MPI_CLK cycle.
User End Setup (UEND to MPI_CLK)
User End Hold (UEND to MPI_CLK)
Data Setup for Read (D[7:0] to MPI_CLK)
Data Hold for Read (D[7:0] from MPI_CLK)
User End to Read Data Delay (UEND to
Data Hold from User Start (low)
Interrupt Request Pulse Width
MPI_STRB
inactive before the end of the read/write cycle.
D[7:0])
(10)
is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and
(5)
Parameter
DD
DD
CS0
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when
(8)
(9)
(continued)
(9)
(7)
(9)
<
(6)
T
<
A
<
T
USTARTCLR_DEL
A
User Logic Delay
70 °C; Industrial: V
<
USTART_DEL
UEND_DEL
UEND_SET
UEND_HLD
TUIRQ_PW
RDS_HLD
RDA_HLD
RDS_SET
RDA_DEL
70 °C; Industrial: V
Symbol
DD
0.00
Min Max Min Max Min Max Min Max
1.0
—
—
—
—
—
—
—
—
—
DD
= 5.0 V ± 10%, –40 °C
–4
= 3.0 V to 3.6 V, –40 °C
3.6
7.5
—
—
—
—
—
—
—
—
—
0.00
0.95
—
—
—
—
—
—
—
—
—
–5
3.4
7.3
—
—
—
—
—
—
—
—
—
Speed
0.00
Lucent Technologies Inc.
0.88
—
—
—
—
—
—
—
—
—
<
T
–6
A
<
<
3.3
7.1
—
—
—
—
—
—
—
—
—
CS0
T
+85 °C.
A
<
and CS1 may go
Data Sheet
0.00
0.75
June 1999
—
—
—
—
—
—
—
—
—
+85 °C.
–7
2.8
6.0
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns