OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 40

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
Input Demultiplexing
The combination of input register capability and the two inputs, IN1 and IN2, from each PIO to the internal routing
provides for input signal demultiplexing without any additional resources. Figure 24 shows the input configuration
and general timing for demultiplexing a multiplexed address and data signal. The PIO input signal is sent to both
the input latch and directly to IN2. The signal is latched on the falling edge of the clock and output to routing at IN1.
The address and data are then both available at the rising edge of the system clock. These signals may be regis-
tered or otherwise processed in the PLCs at that clock edge. Figure 24 also shows the possible use of the SLIC
decoder to perform an address decode to enable which registers are to receive the input data. Although the timing
shown is for using the input register as a latch, it may also be used in the same way as an FF. Also note that the sig-
nals found in PIO inputs IN1 and IN2 can be interchanged.
40
PIO LATCH
PIO INPUT
OUTPUT
OUTPUT
PLC FF
SCLK
ADDR1
SCLK
DATA0
DATA1
PAD
Figure 24. PIO Input Demultiplexing
ADDR2
ADDR2
DATA1
(continued)
DATA2
D
PIO
Q
ADDR3
ADDR3
IN1
IN2
DATA2
DATA3
OTHER ADDRESS
CE
D
LINES
SLIC
ADDR4
PLC
Q
ADDR4
DATA3
DEC
DATA4
ADDR5
Lucent Technologies Inc.
ADDR5
DATA4
Data Sheet
June 1999
5-5798(F)