OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 151

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Data Sheet
June 1999
Lucent Technologies Inc.
Pin Information
Table 67. Pin Descriptions (continued)
Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
Special-Purpose Pins (continued)
MPI_STRB
CS0
Symbol
A[17:0]
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the
activation of all user I/Os) is controlled by a second set of options.
RD
WR
, CS1
/
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
CS0
configuration modes. The FPGA is selected when
uration, a pull-up is enabled.
After configuration, these pins are user-programmable I/O pins (see Note).
RD
a status output. As a status indication, a high indicates ready, and a low indicates busy.
and
This pin is also used as the microprocessor interface ( MPI ) data transfer strobe. For
PowerPC , it is the transfer start (TS). For i960 , it is the address/data strobe (
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
WR
a low on the write strobe,
and
After configuration, this pin is a user-programmable I/O pin (see Note).
During master parallel configuration mode, A[17:0] address the configuration EPROM. In
microprocessor interface ( MPI ) mode, many of the A[n] pins have alternate uses as described
below. See the Special Function Blocks section for more MPI information. During configura-
tion, if not in master parallel or an MPI configuration mode, these pins are 3-stated with a pull-
up enabled.
After configuration, the pins are user-programmable I/O pins (see Note).
(continued)
is used in the asynchronous peripheral configuration mode. A low on
is used in the asynchronous peripheral configuration mode. When the FPGA is selected,
RD
RD
and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor
should not be used simultaneously. If they are, the write strobe overrides.
should not be used simultaneously. If they are, the write strobe overrides.
WR
, loads the data on D[7:0] inputs into an internal data buffer.
Description
CS0
ORCA Series 3C and 3T FPGAs
is low and CS1 is high. During config-
RD
changes D7 into
ADS
).
WR
WR
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