OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 88

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

ORCA Series 3C and 3T FPGAs
FPGA States of Operation
Note: F = finished, no more CLKs required.
88
88
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DONE
DONE
UCLK
DONE
DONE
GSRN
GSRN
GSRN
GSRN
I/O
I/O
I/O
I/O
C1, C2, C3, OR C4
DONE IN
Figure 51. Start-Up Waveforms
C1
C1
C1
C1
C1
Di
Di
U1
U1
U1
DONE IN
U1, U2, U3, OR U4
CCLK_NOSYNC
UCLK_NOSYNC
SYNCHRONIZATION UNCERTAINTY
CCLK_SYNC
UCLK_SYNC
Di + 1
Di + 1
C2
C2
C2
U2
U2
U2
UCLK PERIOD
Di
Di
Di + 2
Di + 2
Di + 1
Di + 1
C3
C3
C3
U3
U3
U3
Di + 2
Di + 2
(continued)
Di + 3
Di + 3
U4
U4
U4
F
C4
C4
F
C4
Di + 3
Di + 3
Di + 4
Di + 4
F
Di + 4
5-2761(F)
F
Reconfiguration
To reconfigure the FPGA when the device is operating
in the system, a low pulse is input into
figuration data in the FPGA is cleared, and the I/Os not
used for configuration are 3-stated. The FPGA then
samples the mode select inputs and begins reconfigu-
ration. When reconfiguration is complete, DONE is
released, allowing it to be pulled high.
Partial Reconfiguration
All ORCA device families have been designed to allow
a partial reconfiguration of the FPGA at any time. This
is done by setting a bit stream option in the previous
configuration sequence that tells the FPGA to not reset
all of the configuration RAM during a reconfiguration.
Then only the configuration frames that are to be modi-
fied need to be rewritten, thereby reducing the configu-
ration time.
Other bit stream options are also available that allow
one portion of the FPGA to remain in operation while a
partial reconfiguration is being done. If this is done, the
user must be careful to not cause contention between
the two configurations (the bit stream resident in the
FPGA and the partial reconfiguration bit stream) as the
second reconfiguration bit stream is being loaded.
Other Configuration Options
There are many other configuration options available to
the user that can be set during bit stream generation in
ORCA Foundry. These include options to enable
boundary scan and/or the microprocessor interface
( MPI ) and/or the programmable clock manager ( PCM ),
readback options, and options to control and use the
internal oscillator after configuration.
Other useful options that affect the next configuration
(not the current configuration process) include options
to disable the global set/reset during configuration, dis-
able the 3-state of I/Os during configuration, and dis-
able the reset of internal RAMs during configuration to
allow for partial configurations (see above). For more
information on how to set these and other configuration
options, please see the ORCA Foundry documenta-
tion.
Lucent Technologies Inc.
PRGM
Data Sheet
June 1999
. The con-