OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 39

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Data Sheet
June 1999
Lucent Technologies Inc.
Programmable Input/Output Cells
Zero-Hold Input
There are two options for zero-hold input capture in the PIO. If input delay mode is selected to delay the signal from
the input pin, data can be either registered or latched with guaranteed zero-hold time in the PIO using a system
clock.
To guarantee zero hold, the system clock spine structure must be used for clocking, as will be discussed later. The
fast zero-hold mode of the PIO input takes advantage of the latch/FF combination and sources the input FF data
from a dedicated latch that is clocked by the ExpressCLK from the PIC. The ExpressCLK is a clock from a dedi-
cated input pin designed for fast, low-skew operation at the I/Os and is described more fully in the Clock Distribu-
tion Network and PIC Interquad (MID) Routing sections that follow. The combination of ExpressCLK latch and
system clock FF guarantees a zero-hold capture of input data in the PIO FF, while at the same time reducing input
setup time. Figure 23 shows a schematic of the fast-capture latch/FF and a sample timing diagram.
Note: CE and LSR signals not shown.
LOCAL SET/RESET
CLOCK ENABLE
EXPRESSCLK
SYSTEM CLK
EXPRESSCLK
INPUT DATA
SYSTEM CLK
INPUT DATA
Q
LATCH
Q
FF
A
Figure 23. Fast-Capture Latch and Timing
A
O
O
I
I
B
A
(continued)
CD = 1
B
LATCH
CLK
D Q
C
B
C
D
CE
ORCA Series 3C and 3T FPGAs
FF
S/R
Q
D
C
D
DATA OUT
TO PIC ROUTING
E
D
E
5-5974(F)
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