OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 110

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

ORCA Series 3C and 3T FPGAs
Timing Characteristics
Table 45. Synchronous Memory Read Characteristics
OR3Cxx Commercial: V
OR3Txxx Commercial: V
Note: The table shows worst-case delays. ORCA Foundry reports the delays for individual paths within a group of paths representing the same
110
Read Operation:
Read Operation, Clocking Data into Latch/FF:
Kz[3:0], F5[A:D]
Data Valid After Address (Kz[3:0] to F[6, 4, 2, 0])
Data Valid After Address (F5[A:D] to F[6, 4, 2, 0])
Address to Clock Setup Time (Kz[3:0] to CLK)
Address to Clock Setup Time (F5[A:D] to CLK)
Address from Clock Hold Time (Kz[3:0] from CLK)
Address from Clock Hold Time (F5[A:D] from CLK)
Clock to PFU Output—Register (CLK to Q[6, 4, 2, 0])
Read Cycle Delay
timing parameter and may accurately report delays that are less than those listed.
F[6, 4, 2, 0]
Q[3:0]
CLK
(T
J
= 85 °C, V
Parameter
DD
DD
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
DD
= min)
(continued)
Figure 66. Synchronous Memory Read Cycle
<
T
<
A
<
T
A
70 °C; Industrial: V
<
SMRD_CYC
70 °C; Industrial: V
REG_DEL
RA4_HLD
RA4_DEL
RA4_SET
RA4_SET
Symbol
RA_HLD
RA_DEL
RA_SET
RA_SET
RA4_DEL
RA_DEL
SMRD_CYC
1.99
1.79
0.00
0.00
Min
—
—
—
—
DD
-4
10.48
DD
= 5.0 V ± 10%, –40 °C
Max
2.34
2.38
2.11
—
—
—
—
REG_DEL
= 3.0 V to 3.6 V, –40 °C
RA4_HLD
RA_HLD
1.47
1.33
0.00
0.00
Min Max Min Max
—
—
—
—
-5
1.80
1.57
1.75
7.66
—
—
—
—
Speed
1.08
1.03
0.00
0.00
—
—
—
—
Lucent Technologies Inc.
<
-6
T
1.32
1.23
1.26
7.53
A
—
—
—
—
<
<
T
+85 °C.
A
0.85
0.81
0.00
0.00
Min
<
—
—
—
—
Data Sheet
June 1999
+85 °C.
-7
Max
1.05
0.99
0.97
5.78
—
—
—
—
5-4622(F)
Unit
ns
ns
ns
ns
ns
ns
ns
ns