OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 109

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Data Sheet
June 1999
Lucent Technologies Inc.
Timing Characteristics
Table 44. Synchronous Memory Write Characteristics
OR3Cxx Commercial: V
OR3Txxx Commercial: V
* The RAM is written on the inactive clock edge following the active edge that latches the address, data, and control signals.
Note: The table shows worst-case delays. ORCA Foundry reports the delays for individual paths within a group of paths representing the same
Write Operation for RAM Mode:
Write Operation Setup Time:
Write Operation Hold Time:
CIN, DIN[7, 5, 3, 1]
Maximum Frequency
Clock Low Time
Clock High Time
Clock to Data Valid (CLK to F[6, 4, 2, 0])*
Address to Clock (CIN to CLK)
Address to Clock (DIN[7, 5, 3, 1] to CLK)
Data to Clock (DIN[6, 4, 2, 0] to CLK)
Write Enable (WREN) to Clock (ASWE to CLK)
Write-port Enable 0 (WPE0) to Clock (CE to
Write-port Enable 1 (WPE1) to Clock (LSR to
Address from Clock (CIN from CLK)
Address from Clock (DIN[7, 5, 3, 1] from CLK)
Data from Clock (DIN[6, 4, 2, 0] from CLK)
Write Enable (WREN) from Clock (ASWE from
Write-port Enable 0 (WPE0) from Clock (CE
Write-port Enable 1 (WPE1) from Clock (LSR
CLK)
CLK)
CLK)
from CLK)
from CLK)
ASWE (WREN)
timing parameter and may accurately report delays that are less than those listed.
DIN[6, 4, 2, 0]
LSR (WPE1)
CE (WPE0),
F[6, 4, 2, 0]
CK
Parameter
DD
DD
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
Figure 65. Synchronous Memory Write Characteristics
WPE0_SET
WPE1_SET
(continued)
WE_SET
T
SCH
<
SMCLKH_MPW
SMCLKL_MPW
SMCLK_FRQ
WPE0_SET
WPE1_SET
WPE0_HLD
WPE1_HLD
T
MEM_DEL
WA4_SET
WA4_HLD
WA4_SET
<
WD_SET
WE_SET
WA_HLD
WD_HLD
WE_HLD
A
WA_SET
WA_SET
WD_SET
Symbol
<
T
A
70 °C; Industrial: V
<
70 °C; Industrial: V
2.34
3.79
1.25
0.72
0.02
0.18
2.25
2.79
0.00
0.00
0.59
0.03
0.00
0.00
Min
—
—
-4
151.00
10.00
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WA4_HLD
WA_HLD
WD_HLD
WE_HLD
WPE0_HLD
WPE1_HLD
DD
DD
= 5.0 V ± 10%, –40 °C
1.80
2.77
0.99
0.52
0.06
0.16
1.69
2.13
0.00
0.00
0.42
0.00
0.00
0.00
Min
= 3.0 V to 3.6 V, –40 °C
—
—
T
ORCA Series 3C and 3T FPGAs
SCL
MEM_DEL
-5
197.00
Max
7.14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Speed
1.32
2.13
0.71
0.35
0.00
0.14
1.16
1.58
0.00
0.00
0.40
0.08
0.00
0.00
Min
—
—
<
-6
254.00
T
Max
5.00
A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
<
<
T
+85 °C.
A
<
1.05
1.62
0.58
0.28
0.00
0.12
0.84
1.31
0.00
0.00
0.32
0.06
0.00
0.00
Min
—
—
+85 °C.
-7
315.00
Max
4.08
—
—
—
—
—
—
—
—
—
—
—
—
5-4621(F)
109
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns