OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 69

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Data Sheet
June 1999
Lucent Technologies Inc.
Microprocessor Interface (MPI)
Scratchpad Register
The MPI scratchpad register is an 8-bit read/write register with no defined operation. It may be used for any user-
defined function.
Control Register 2
The MPI control register 2 is a read/write register. The host processor writes a control byte to configure the MPI . It
is readable by the host processor to verify the status of control bits it had previously written.
Table 21. MPI Control Register 2
Bit #
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
MP_HOLD_BUS Enable Bus Holding During Daisy-Chain Configuration Mode. Setting this bit to
EN_IRQ_CFG
EN_IRQ_ERR
EN_IRQ_USR
MP_DAISY
MP_USER
Bit Name
Reserved
Reserved
Enable
Mode. Setting this bit to a 1 prior to configuration enables the
when new data is requested for configuration writes or is available for configuration
reads to/from the configuration data register. A 0 clears the
only valid for daisy-chain configuration. Default = 0.
Enable
enables the
configuration. A 0 clears the
tion mode. Default = 0.
Enable
circuitry in the FPGA to generate an interrupt to the host processor by sourcing a
logic low on the
MPI Daisy-Chain Output Enable. Setting this bit to a 1 enables daisy-chain output
of the configuration data. See the Configuration section of this data sheet for daisy-
chain configuration details. Default = 0.
a 1 will cause the MPI to wait until the FPGA configuration logic has serialized a
byte of configuration data before acknowledging the transaction. The data is only
serialized if the MP_DAISY (bit 3 above) control bit is set to 1. If MP_HOLD_BUS is
set to 0, the MPI will immediately acknowledge a configuration data byte transfer.
Immediate acknowledgment allows the host processor to perform other tasks during
FPGA configuration by polling the MPI status register (or by interrupt) and only write
configuration data when the FPGA is ready. Default = 0.
MPI User Mode Enable. Setting this bit to a 1 will enable the MPI for user mode
operation. MP_USER must be set prior to the FPGA DONE signal going high during
configuration. The MPI may also be enabled for user operation via the configuration
bit stream. Default = 0.
IRQ
IRQ
IRQ
from the User FPGA Space. Setting this bit to a 1 allows user-defined
for Configuration Data Request in Daisy-Chain Configuration
for Bit Stream Error. Setting this bit to a 1 prior to configuration
IRQ
(continued)
UIRQ
signal to go active on the occurrence of a bit stream error during
signal in the user logic. Default = 0.
IRQ
enable. This bit only has effect while in configura-
Description
—
—
ORCA Series 3C and 3T FPGAs
IRQ
IRQ
enable. This bit is
signal to go active
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