OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 45

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Data Sheet
June 1999
Programmable Input/Output Cells
(continued)
PIC Architectural Description
The PIC architecture as seen in ORCA Foundry is
shown in Figure 27. The figure is the left PIC of a PIC
pair on the top edge of a Series 3 array. Both PICs in a
pair are similar, with the differences mainly lying in the
connections between the PIC switching segments
(pSW), the IN2 connections across PIC boundaries,
and the system clock spine driver residing in only one
PIC of a pair.
A. This is a programmable input/output (PIO). There
B. This is the PIC output switching block. It connects
C. This is the system clock spine switching block and
D. PIC switching segments (pSW). These routing seg-
E. px1 routing segments. The PIC x1 routing seg-
F. px2 routing segments. The PICs have routing that
G. px5 routing segments. Each of the ten PIC x5 rout-
H. pxH routing segments. The eight PIC xH routing
I. (Not used intentionally for clarity.)
J. pxL routing segments. The PIC long lines run the
K. x5 routing segments from the adjacent PLC routing.
L. xL routing segments from the adjacent PLC routing.
M. x1 routing segments from the adjacent PLC routing.
N. Switching segments from the adjacent PLC routing.
Lucent Technologies Inc.
are four PIOs per PIC. The PIOs contain the PIC
logic and I/O buffers.
the PIC switching segments and local clock lines to
the PIO output and control signals.
buffer. There is only one system clock spine per pair
of PICs. Its inputs can come from the PIC switching
segments or any of the eight PIO inputs in a PIC
pair.
ments are used to interconnect routing resources
within the PIC and to a lesser degree, between
PICs.
ments traverse one PIC and break at a CIP in the
middle of each PIC.
traverses two PICs between breaks. The breaks are
staggered among the five px2 segments.
ing segments traverses five PICs in between breaks
at a CIP. Two px5 segments break in each PIC.
segments traverse half of the array and break at
CIPs in the interquad routing region that is in the
middle of the array.
entire length of the side of the array.
O. xH routing segments from the adjacent PLC routing.
P. BIDI routing segments from the adjacent PLC rout-
Q. These are the IN2 routing segments. There is one
R. These CIPs connect the IN1 and IN2 routing seg-
S. These CIPs break the PIC switching segments at
T. These CIPs connect adjacent PLC routing
U. These CIPs connect inter-PIC routing with the PIC
V. These CIPs break the px1, px2, and px5 routing at
W. These mutually exclusive buffers can drive one long
X. These mutually exclusive buffers can select a
Y. These are the four local system clock routing seg-
Z. These mutually exclusive buffers allow a signal on
AA. ExpressCLK routing line.
AB. System clock spine.
AC. These various groups of CIPs connect routing
AD. These buffers provide connectivity between the
AE. These mutually exclusive buffers and CIPs provide
AF. These buffers allow the IN2 signals to drive onto
ing.
IN2 line from each PIO, and all eight IN2 lines from
each PIC pair are present in both PICs of a pair.
ments from the PIOs to the PIC switching seg-
ments.
the interface between a PIC pair.
resources to the PIC switching segments.
switching segments.
the middle of a PIC. The px2 and px5 CIP place-
ment varies depending on the PLC.
line signal onto a PIC local clock routing segment.
source from one of the local system clock routes to
drive the PIO 3-state control signal.
ments. Two come from connections within the PIC,
one from the other PIC in the pair, and one from the
adjacent PLC.
the PIC switching segments to be routed to a sys-
tem clock spine or to a PIO system clock.
resources from the adjacent PLC to the inter-PIC
routing resources.
PLC xL (xH) lines and the PIC xL (xH) lines or
connectivity between one of the IN2 routing seg-
ments and the PIC and/or PLC xL (xH) routing
segments.
connectivity to the PLC xL and xH lines from one
of the IN2 input segments.
the BIDI routing of the adjacent PLC, or the BIDI
routing of the adjacent PLC, and the PIC switching
segments and/or PIC half lines may be connected.
ORCA Series 3C and 3T FPGAs
45