OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 65

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Data Sheet
June 1999
Microprocessor Interface (MPI)
PowerPC System
In Figure 43, the ORCA FPGA is a memory-mapped
peripheral to the PowerPC processor. The PowerPC
interface uses separate address and data buses and
has several control lines. The ORCA chip select lines,
CS0
coming from the PowerPC . In this manner, the FPGA is
capable of a transaction with the PowerPC whenever
the address line connected to
line for CS1 is high, and there is a valid address on
PowerPC address lines A[27:31]. Other forms of selec-
tion are possible by using the FPGA chip selects in a
different way. For example, PowerPC address bits
A[0:26] could be decoded to select
the FPGA is the only peripheral to the PowerPC , CS0
and CS1 could be tied low and high, respectively, to
cause them to always be selected. If the MPI is not
used for FPGA configuration, decoding logic can be
implemented internal or external to the FPGA. If logic
internal to the FPGA is used, the chip selects must be
routed out on an output pin and then connected exter-
nally to
configuration, any decode logic used must be imple-
mented external to the FPGA since the FPGA logic has
not been configured yet.
Note: FPGA shown as a memory-mapped peripheral using
Lucent Technologies Inc.
The basic flow of a transaction on the PowerPC / MPI
interface is given below. Pin descriptions are shown in
Table 16 and timing is shown in the Timing Characteris-
tics section of this data sheet. For both read and write
transactions, the address, chip select, and read/write
POWERPC
and CS1, are each connected to an address line
CS1. Other decoding schemes are possible using
CS1.
CS0
CLKOUT
A[27:31]
RD/WR
D[7:0]
IRQx
and/or CS1. If the MPI is to be used for
A26
A25
TA
TS
BI
Figure 43. PowerPC /MPI
8
D[7:0]
A[4:0]
MPI_CLK
MPI_RW
MPI_ACK
MPI_BI
MPI_IRQ
MPI_STRB
CS0
CS1
CS0
SERIES 3
is low, the address
ORCA
FPGA
CS0
DOUT
DONE
CCLK
HDC
LDC
INIT
and CS1, or if
(continued)
TO DAISY-
CHAINED
DEVICES
CS0
CS0
5-5761(F)
and/or
and
Interrupt requests can be sent to the PowerPC asyn-
chronously to the read/write process. Interrupt requests
are sourced by the user-logic in the FPGA. The MPI will
assert the request to the PowerPC as a direct interrupt
signal and/or a pollable bit in the MPI status register
(discussed in the MPI Setup and Control section). The
MPI will continue to assert the interrupt request until
the user-logic deasserts its interrupt request signal.
Table 16. PowerPC /MPI Configuration
acknowledged to the PowerPC by the low asser tion of
(read high, write low) signals are set up at the FPGA
pins by the PowerPC . The PowerPC then asserts its
transfer start signal (
clock cycle during which
support burst transfers, so the burst inhibit signal,
also asserted low during the transfer acknowledge . The
same process applies to a read from the MPI except
that the read data is expected at the FPGA data pins by
the PowerPC at the rising edge of the clock when
low. The MPI only drives
MPI during a write at the rising clock edge after the
the
PowerPC
CLKOUT
A[27:31]
IRQ [7:0]
RD/ WR
Signal
Any of
D[0:7]
TA
TS
TA
—
—
BI
signal. The MPI PowerPC interface does not
RD/MPI_STRB
A11/ MPI_IRQ
A7/MPI_CLK
A9/ MPI_ACK
A8/MPI_RW
A10/ MPI_BI
ORCA Series 3C and 3T FPGAs
ORCA Pin
Name
D[7:0]
A[4:0]
CS1
CS0
TS
) low. Data is available to the
TS
TA
low for one clock cycle.
is low. The transfer is
MPI
I/O
I/O
O
O
O
I
I
I
I
I
I
8-bit data bus
5-bit
bus
Transfer start signal
Active-low
select
Active-high
select
PowerPC interface
clock
Read (high)/write
(low) signal
Active-low transfer
acknowledge signal
Active-low burst
transfer inhibit
signal
Active-low interrupt
request signal
MPI
Function
address
MPI
MPI
BI
TA
, is
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is