OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 86

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

ORCA Series 3C and 3T FPGAs
FPGA States of Operation
If configuration has begun, an assertion of
PRGM
tialization state. The
pulled back high before the FPGA will enter the config-
uration state. During the start-up and operating states,
only the assertion of
In the master configuration modes, the FPGA is the
source of configuration clock (CCLK). In this mode, the
initialization state is extended to ensure that, in daisy-
chain operation, all daisy-chained slave devices are
ready. Independent of differences in clock rates, master
mode devices remain in the initialization state an addi-
tional six internal clock cycles after
When configuration is initiated, a counter in the FPGA
is set to 0 and begins to count configuration clock
cycles applied to the FPGA. As each configuration data
frame is supplied to the FPGA, it is internally assem-
bled into data words. Each data word is loaded into the
internal configuration memory. The configuration load-
ing process is complete when the internal length count
equals the loaded length count in the length count field,
and the required end of configuration frame is written.
All OR3Cxx I/Os operate as TTL inputs during configu-
ration (OR3Txxx I/Os are CMOS-only). All I/Os that are
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initiates an abort, returning the FPGA to the ini-
PRGM
PRGM
INTERNAL
USER I/O
RESET
(gsrn)
RESET
PRGM
M[3:0]
DONE
CCLK
Figure 50. Initialization/Configuration/Start-Up Waveforms
HDC
LDC
INIT
V
and
DD
causes a reconfiguration.
RESET
INIT
(continued)
pins must be
goes high.
RESET
INITIALIZATION
or
not used during the configuration process are
3-stated with internal pull-ups.
Warning: During configuration, all OR3Txxx inputs
have internal pull-ups enabled. If these inputs are
driven to 5V, they will draw substantial current ( 5 ma).
This is due to the fact that the inputs are pulled up to
3V.
During configuration, the PIC and PLC latches/FFs are
held set/reset and the internal BIDI buffers are 3-
stated. The combinatorial logic begins to function as
the FPGA is configured. Figure 50 shows the general
waveform of the initialization, configuration, and start-
up states.
Configuration
The ORCA Series FPGA functionality is determined by
the state of internal configuration RAM. This configura-
tion RAM can be loaded in a number of different
modes. In these configuration modes, the FPGA can
act as a master or a slave of other devices in the sys-
tem. The decision as to which configuration mode to
use is a system design issue. Configuration is dis-
cussed in detail, including the configuration data format
and the configuration modes used to load the configu-
ration data in the FPGA, following a description of the
start-up state.
CONFIGURATION
OPERATION
START-UP
Lucent Technologies Inc.
Data Sheet
June 1999
5-4482(F)