OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 137

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Data Sheet
June 1999
Lucent Technologies Inc.
Timing Characteristics
Table 62 . Master Parallel Configuration Mode Timing Characteristics
OR3Cxx Commercial: V
OR3Txxx Commercial: V
Notes:
The RCLK period consists of seven CCLKs for RCLK low and one CCLK for RCLK high.
Serial data is transmitted out on DOUT 1.5 CCLK cycles after the byte is input on D[7:0].
A[17:0]
RCLK to Address Valid
D[7:0] Setup Time to RCLK High
D[7:0] Hold Time to RCLK High
RCLK Low Time (M3 = 0)
RCLK High Time (M3 = 0)
RCLK Low Time (M3 = 1)
RCLK High Time (M3 = 1)
CCLK to DOUT
DOUT
RCLK
D[7:0]
CCLK
Parameter
T
AV
DD
DD
Figure 84. Master Parallel Configuration Mode Timing Diagram
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
(continued)
T
S
BYTE N
<
T
Symbol
<
A
T
T
T
T
T
T
T
T
<
T
CH
CH
AV
CL
CL
A
S
H
D
70 °C; Industrial: V
<
T
CH
70 °C; Industrial: V
T
H
T
D
D0
60.00
0.00
7.00
1.00
7.00
1.00
Min
—
—
DD
D1
DD
= 5.0 V ± 10%, –40 °C
= 3.0 V to 3.6 V, –40 °C
ORCA Series 3C and 3T FPGAs
D2
T
CL
BYTE N + 1
D3
60.00
Max
7.00
1.00
7.00
1.00
5.00
D4
—
—
D5
<
T
A
<
D6
<
T
+85 °C.
A
CCLK cycles
CCLK cycles
CCLK cycles
CCLK cycles
<
D7
+85 °C.
Unit
ns
ns
ns
ns
5-6764(F)
137