OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 66

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI)
i960 System
Figure 44 shows a schematic for connecting the ORCA
MPI to supported i960 processors. In the figure, the
FPGA is shown as the only peripheral, with the FPGA
chip select lines,
respectively. The i960 address and data are multi-
plexed onto the same bus. This precludes memory
mapping of the FPGA in the i960 memory space of a
multiperipheral system without some form of address
latching to capture and hold the address signals to
drive the
nals could also be decoded and latched to drive the
CS0
FPGA configuration, decoding/latching logic can be
implemented internal or external to the FPGA. If logic
internal to the FPGA is used, the chip selects must be
routed out an output pin and then connected externally
to
ration, any decode/latch logic used must be imple-
mented external to the FPGA since the FPGA logic has
not been configured yet.
Note: FPGA shown as only system peripheral with fixed-chip select
The basic flow of a transaction on the i960 / MPI inter-
face is given below. Pin descriptions are shown in
Table 17, and timing is shown in the ORCA Timing
Characteristics section of this data sheet. For both read
and write transactions, the address latch enable (ALE)
is set up by the i960 at the FPGA to the falling edge of
the clock. The address, byte enables, chip selects, and
read/write (read low, write high) signals are normally
66
66
i960 SYSTEM CLOCK
CS0
i960
and/or CS1 signals. If the MPI is not used for
signals. For multiperipheral systems, address decoding and/
or latching can be used to implement chip selects.
and/or CS1. If the MPI is to be used for configu-
RDYRCV
CS0
AD[7:0]
CLKIN
XINTx
ADS
W/R
ALE
BE0
BE1
and/or CS1 signals. Multiple address sig-
CS0
Figure 44. i960 /MPI
V
8
DD
and CS1, tied low and high,
D[7:0]
MPI_CLK
MPI_RW
MPI_ACK
MPI_IRQ
MPI_ALE
MPI_STRB
MPI_BE0
MPI_BE1
CS1
CS0
SERIES 3
ORCA
FPGA
DONE
DOUT
CCLK
HDC
LDC
INIT
(continued)
TO DAISY-
CHAINED
DEVICES
5-5762(F)
set up at the FPGA pins by the i960 at the next rising
edge of the clock. At this same rising clock edge, the
i960 asserts its address/data strobe (
available to the MPI during a write at the rising clock
edge of the following clock cycle. The transfer is
acknowledged to the i960 by the low assertion of the
ready/recover (
applies to a read from the MPI except that the read
data is expected at the FPGA data pins by the i960 at
the rising edge of the clock when
MPI only drives
Interrupts can be sent to the i960 asynchronously to
the read/write process. Interrupt requests are sourced
by the user-logic in the FPGA. The MPI will assert the
request to the i960 as a direct interrupt signal and/or a
pollable bit in the MPI status register (discussed in the
MPI Setup and Control section). The MPI will continue
to assert the interrupt request until the user-logic deas-
serts its interrupt request signal.
Table 17. i960 /MPI Configuration
XINT [7:0]
RDYRCV
Signal
AD[7:0]
System
Any of
Clock
i960
ADS
W/ R
ALE
BE0
BE1
—
—
A8/MPI_RW
ORCA Pin
RDY/RCLK/
MPI_STRB
MPI_ALE
MPI_CLK
MPI_ACK
MPI_BE0
MPI_BE1
MPI_IRQ
Name
D[7:0]
RDYRCV
A11/
CS0
CS1
RD /
A7/
A9/
A0/
A1/
RDYRCV
) signal. The same process
MPI
low for one clock cycle.
I/O
I/O
O
O
I
I
I
I
I
I
I
I
Lucent Technologies Inc.
Multiplexed 5-bit address/
8-bit data bus. The
address appears on D[4:0].
Address latch enable used
to capture address from
AD[4:0] on falling edge of
clock.
Address/data strobe to
indicate start of transac-
tion.
Active-low
Active-high
i960 system clock. This
clock is sourced by the
system and not the i960 .
Write (high)/read (low)
signal.
Active-low ready/recover
signal indicating acknowl-
edgment of the transac-
tion.
Active-low interrupt
request signal.
Byte-enable 0 used as
address bit 0 in i960 8-bit
mode.
Byte-enable 1 used as
address bit 1 in i960 8-bit
mode.
RDYRCV
ADS
Function
MPI
MPI
Data Sheet
) low. Data is
June 1999
is low. The
select.
select.