MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 85

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

overflow), the SDT RX_SAR’s write pointer is adjusted such that the cell is written to the circular buffer at the
location of the pre-calculated slip pointer. In addition, when slips are detected, the corresponding MIB statistics
fields (Buffer Underruns or Buffer Overflows) in the active VC’s SDT Reassembly Control Structure are
incremented.
SDT Received Cell Counter
The SDT RX_SAR also provides the user with the number of SDT cells received from the UTOPIA block. This 16-
bit counter value can be viewed in register SRCCR at address 2048h. This counter is an overall SDT cell counter: it
is incremented every time an SDT cell is received from the UTOPIA (regardless of whether the cells are discarded
by the SDT RX_SAR). When this counter rolls over, a status bit gets set in the SRCSR register at address 2046h.
This status bit can be cleared by software. This rollover condition can also generate a service request to the CPU if
the corresponding service enable bit is set.
The user is also provided with a per-VC cell counter. This counter is located in the SDT Reassembly Control
Structure (see Figure 28 on page 70). The operation of this counter is similar to the overall SDT cell counter. When
the per-VC counter rolls over, a status bit gets set in the control structure and can be cleared by the user. The
rollover condition can also generate a request to the CPU if the SDT_REAS_ROLL_SE bit is set in the SRSER
register at address 2042h. The CPU can then read the contents of the SERVICE_ADD field of the SRSR register at
address 2044h to identify which control structure generated the service request.
Complete Reassembly Data Flow Overview
The following figures give a top-level view of the data flow in the reassembly direction within the MT90520
device.
Figure 30 shows the complete segmentation data path in UDT mode, from the incoming TDM data bus to the
outgoing UTOPIA data bus, whereas Figure 31 shows the complete segmentation data path in SDT mode.
UTO_IN_ENBATM_CLAVPHY
UTO_IN_CLAVATM_ENBPHY
UTO_IN_DATA[15:0]
UTO_IN_SOC
UTO_IN_PAR
UTO_IN_CLK
Figure 30 - Overview of CBR Data Reassembly Process (UDT Mode)
MT90520
UTOPIA Module
UTOPIA
FIFO
RX
Zarlink Semiconductor Inc.
MT90520
UDT Reassembly
Control Structure
internal memory)
(one per port in
RX_SAR
UDT
85
Reassembly
int. memory)
Buffer (one
per port in
Circular
UDT
Module (one per
TDM Interface
Output
Buffer
TDM
port)
Data Sheet
DSTo
LOSo
SToCLK
.