MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 134
MT90520AG
Manufacturer Part Number
MT90520AG
Description
8-Port Primary Rate Circuit Emulation AAL1 SAR
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.MT90520AG.pdf
(180 pages)
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Address: 400C (Hex)
Label: UVPME
Reset Value: 0000 (Hex)
Address: 400E (Hex)
Label: UPM
Reset Value: 0000 (Hex)
Address: 4010 (Hex)
Label: UFS
Reset Value: 0030 (Hex)
UTO_OUT_FIFO_
UTO_OUT_FIFO_
VP_MATCH_ENB
UTO_OUT_FIFO
UTO_IN_FIFO_
UTO_IN_FIFO_
UTO_IN_FIFO_
MISMATCHES
LOOPBACK
Reserved
PARITY_
UTOPIA_
Reserved
EMPTY
EMPTY
RESET
RESET
Label
Label
Label
FULL
FULL
Position
Position
Position
15:12
11:0
15:0
15:7
Bit
Bit
Bit
0
1
2
3
4
5
6
Table 66 - UTOPIA Parity Mismatches Register
Type
Type
Type
R/W
R/W
R/W
R/W
R/O
R/O
R/O
R/O
R/O
R/O
R/O
Table 67 - UTOPIA FIFO Status Register
Table 65 - VP Match Enable Register
Each bit, when set, enables the comparison of a cell’s VPI and the corresponding
VP_MATCH bit. If a bit in this register is not set, the corresponding bit in the received cell
VPI is considered valid, regardless of the setting in the VP_MATCH field. In UNI mode,
bits<11:8> should be cleared to avoid the comparison of the GFC.
Always reads “0000”.
Contains a count of the mismatches between UTO_IN_DATA and UTO_IN_PARITY. If this
counter rolls over, the PARITY_ROLL_STATUS bit in the UTOPIA Status Register at
4012h will be set.
When set, this bit forces the UTOPIA port into loopback mode. Data is looped from the
incoming UTOPIA bus to the outgoing UTOPIA bus, through the incoming UTOPIA FIFO
and the outgoing UTOPIA FIFO. The incoming data is filtered by the Match and Match
Enable filters before being re-transmitted.
When set, empties the outgoing UTOPIA FIFO.
When set, empties the incoming UTOPIA FIFO.
If set, this bit indicates that the outgoing UTOPIA FIFO is full.
If set, this bit indicates that the outgoing UTOPIA FIFO is empty.
If set, this bit indicates that the incoming UTOPIA FIFO is empty.
If set, this bit indicates that the incoming UTOPIA FIFO is full.
Always reads “0000_0000_0”.
Zarlink Semiconductor Inc.
MT90520
134
Description
Description
Description
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