MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 131

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

6.2.7
Address: 4000 (Hex)
Label: UCR
Reset Value: 0004 (Hex)
Address: 3200 + p*2 (Hex)
Label: TCR_Pp (where p represents the port number)
Reset Value: 07FF (Hex)
LATE_CELL_ SE
LATE_CELL_
LATE_CELL_
CUT_VC_SE
UTO_CLK_SEL
CUT_VC_
Reserved
SDT_N_UDT
PERIOD
STATUS
STATUS
UNI_N_NNI
Label
UTOPIA Interface Module
Label
Position
10:0
Bit
11
12
13
14
15
Position
Bit
Table 58 - Timeout Configuration Register (one per port)
0
1
2
R/O/L
R/O/L
Type
R/W
R/W
R/W
R/O
Table 59 - UTOPIA Configuration Register
Type
R/W
R/W
R/W
Late Cell Timeout.
If a cell has not been received prior to this timeout (measured in 125 µs increments), an
internal flag is set, indicating a late cell arrival. This timer should generally be set to a value
equal to the cell assembly time, plus the expected CDV. Default: 256 ms
In UDT mode, if this timeout period is passed, the LATE_CELL_STATUS bit in this per-port
register will be set. Additionally, if the CHECK_LATE_ARRIVALS bit is set in the UDT
Reassembly Control Register at 2000h, a dummy cell will also be inserted into the UDT
Reassembly Circular Buffer for the port.
Late Cell Status Service Enable.
When
RX_TIMEOUT_SRV bit to be set in the Main Status Register at 0002h. As well, the per-
port status bit for the corresponding port will be set in the MIB Timeout Status Register at
3002h.
If set, indicates that a late cell event has occurred on this port. This bit can be cleared by
writing with ‘0’. Note: This bit will only be set if a port is operating in UDT mode.
Cut VC Status Service Enable.
When set, a ‘1’ on CUT_VC_STATUS in this register will cause the RX_TIMEOUT_SRV
bit to be set in the Main Status Register at 0002h. As well, the per-port status bit for the
corresponding port will be set in the MIB Timeout Status Register at 3002h.
If set, indicates that a cut VC event has occurred on this port (i.e, the CUT_VC_PERIOD
set in the MIB Timeout Configuration Register at 3000h has been passed without a cell
arrival). This bit can be cleared by writing with ‘0’.
Always reads ‘0’.
SDT/UDT.
Selects between SDT mode (when set) and UDT mode (when cleared). To operate in
both modes simultaneously, this bit must be cleared. When operating in UDT mode, the
UDT VCI/VPI comparison is performed followed by the LUT (if necessary). In SDT mode,
the look-up is performed first (the UDT VPI/VCI comparison is skipped).
UNI/NNI.
Selects between UNI (when set) and NNI mode (when cleared). If NNI mode is enabled,
the GFC field of the cell header will be used in the UDT VPI/VCI comparison.
Selects between an external clock (when set) and an internal clock (when cleared). If an
internal clock is selected, UTO_IN_CLK and UTO_OUT_CLK are outputs, and the
frequency of the generated clock is equivalent to MCLK/2. If an external clock is
selected, UTO_IN_CLK and UTO_OUT_CLK are inputs.
Zarlink Semiconductor Inc.
set,
MT90520
a
‘1’
131
on
LATE_CELL_STATUS
Description
Description
in
this
register
will
Data Sheet
cause
the