MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 139

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 5200 + p*10 (Hex)
Label: CCR_Pp (where p represents the port number)
Reset Value: 0000 (Hex)
PLL_MODE_SEL
PLL_FREQ_SEL
FNXISEL
CLKSEL
RTSSEL
Label
Position
8:7
Bit
1:0
3:2
6:5
4
Table 75 - Clocking Configuration Register (one per port)
Type
R/W
R/W
R/W
R/W
R/W
SToCLK Selector.
These bits are used to select the source for the port’s SToCLK output signal:
“00” = MCLK/2
“01” = STiCLK
“10” = PLLCLK (generated by the port’s internal PLL)
“11” = common clock; sourced from either the TDM_CLK input pin (if the EXT_N_INT bit is
set in the Clock Management Configuration Register at 5000h) or from an internal version
of the output signal PRI_REF (if the EXT_N_INT bit is cleared).
Note: If there is an LOS signal received on this port and the user has selected to source
SToCLK from STiCLK, the user’s configuration will be overridden and SToCLK will be
sourced from PLLCLK.
RTS Clock Selector.
These bits are used to select the source for the internal RTS clock:
“00” = STiCLK (used when transmitting RTS in independent mode or in ST-BUS
backplane mode)
“01” = C4M_C2M (used when transmitting RTS in Generic backplane mode)
“10” = PLLCLK (used when receiving RTS & performing clock recovery)
“11” = Reserved.
Note: When transmitting RTS from a TDM port that is operating in ST-BUS backplane
mode, it is necessary to present a bit-rate clock to the Tx SRTS circuitry. The user must
provide this clock by presenting a 2.048 MHz clock on the STiCLK input of the
transmitting port. Due to this restriction, the C4M_C2M backplane clock must be
either an input (“slave” mode), or it must be generated from a reference source
other than this port’s STiCLK input.
FNXI Source Selector.
This bit is used to select either the FNXI1 or the FNXI2 clock rate for RTS generation or
comparison:
‘0’ = FNXI1_RATE
‘1’ = FNXI2_RATE.
Output Frequency Selector for Internal PLL.
“00” = 1.544 MHz
“01” = 2.048 MHz
“10” = 4.096 MHz
“11” = Reserved.
Operating Mode for Internal PLL.
These bits define the operating mode of the PLL.
“00” = Normal mode; output synchronized to the input.
“01” = Holdover mode; output no longer follows the input, but holds last frequency setting.
“10” = Freerun mode; output is fixed to the nominal frequency.
“11” = CPU mode; the output frequency is directly controlled by the programmable
DCO_DIFF_p value, regardless of PLL_INPUT_SEL.
Zarlink Semiconductor Inc.
MT90520
139
Description
Data Sheet