MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 14

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

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Supports AAL1 Trunking as per af-vtoa-0089.000:
High-capacity AAL1 CES SAR device with 8 primary rate TDM ports operating at DS1 or E1 rates.
Supports major modes of Circuit Emulation Services (CES) for DS1 and E1 as per af-vtoa-0078.000:
Compliant with ITU-T Rec. I.363.1
Supports mixed DS1/E1 operation
Supports mixed UDT/SDT operation
Total clock recovery solution integrated on-chip
Supports non-CBR data cells and OAM cells destined for microprocessor with Transmit and Receive Data
Cell Buffer.
16-bit microprocessor port, configurable to Motorola or Intel timing
Indirect reads and writes possible to internal and external memory block.
Programmable interrupts for control and statistics
Allows access to internal registers and memory for initialization, control, and statistics
Allows access to external RAM for initialization, control, and observation
Supports common, commercially-available, no-latency flow-through and pipelined synchronous SRAM (ZBT,
NoBL, NtRAM)
Supports common SSRAM memory sizes - 128 K x 16, 256 K x16, 512 K x 16 and 1 M x 16; 128 K x 18,
256 K x 18, 512 K x 18 and 1 M x 18 (parity is optional)
Flexible TDM port allows operation with a wide selection of framers, LIUs, switches and multiplexers.
Eight independently-timed, highly configurable, TDM interfaces can operate using:
Supports up to 256 bidirectional TDM channels.
UTOPIA Level 2 compliant 16-bit or 8-bit bus, capable of running at up to 52 MHz
• Logical Nx64 Structured Service, using 2.048 Mbps TDM bus
• DS1 Nx64 Basic Service
• DS1 Nx64 Service with CAS
• E1 Nx64 Basic Service
• E1 Nx64 Service with CAS
• DS1 Unstructured Service
• E1 Unstructured Service
• Up to 128 TDM channels can be carried per VCC (up to 256 TDM channels per device).
• bit-clock rate (Unstructured CES)
• framed ST-BUS or Generic TDM bus (Structured CES - independent mode)
• common TDM backplane clock using ST-BUS or Generic TDM bus (Structured CES - backplane mode).
• Accepts data rate of up to 622 Mbps
• Supports both “master” (ATM-end) and “slave” (PHY-end) operation
• Supports multi-PHY (MPHY) mode when operating as a PHY device
Key Functionality
Microprocessor Interface
External Memory Interface
TDM Interface
UTOPIA Interface
Features
Zarlink Semiconductor Inc.
MT90520
14
Data Sheet