MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 150

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

7.2
MCLK - Master Clock Input Parameters
PHY_CLK - Clock Input Parameters
7.2.1
Intel Microprocessor Interface Timing - Read Cycle Parameters
MCLK Frequency
MCLK Period
MCLK Pulse Width (HIGH / LOW)
PHY_CLK Frequency
PHY_CLK Period
PHY_CLK Pulse Width (HIGH / LOW)
Address Setup - (AEM and CPU_ADD[20:1]
VALID) to (CS and RD asserted)
Address Hold - (CS or RD de-asserted) to
(AEM and CPU_ADD[20:1] INVALID)
RDY Low - CS asserted to RDY driven low
RDY Delay - (CS and RD asserted) to RDY
asserted
RDY High-Impedance - CS de-asserted to
RDY high-impedance
Data Output Setup - CPU_DATA[15:0]
VALID to RDY asserted
Data Output Hold - (CS or RD de-asserted)
to CPU_DATA[15:0] INVALID
Note 1: MCLK = 66 MHz (15.2 ns)
Note 2: Both CS and RD must be asserted for a read cycle to occur. A read cycle is completed when either CS or RD is de-asserted.
Note 3: There should be a minimum of 3 MCLK periods between CPU accesses, to allow the MT90520 to recognize the accesses as
separate (i.e., CS must be de-asserted for 3 MCLK cycles between CPU accesses).
19.44 MHz
8 kHz
19.44 MHz
8 kHz
Register access
Memory access
AC Characteristics
CPU Interface
Characteristic
Characteristic
Characteristic
Sym.
t
MH/L
t
t
MF
MP
Sym.
t
PH/L
t
t
PF
PP
t
t
t
t
t
RRDYZ
Sym.
RRDYL
ADDS
ADDH
RACC
t
t
DS
DH
Min.
6.8
Zarlink Semiconductor Inc.
Min.
0.1
20
MT90520
Min.
197
213
0
0
0
0
0
19.44
51.44
25.72
Typ.
66.0
15.2
Typ.
62.5
7.6
125
150
8
Typ.
228
Max.
16
Max.
66.0
Units
MHz
kHz
Max.
2021
ns
µs
ns
µs
243
10
10
Units
MHz
ns
ns
PHY_CLK frequency determined by
8_KHZ_SEL bit in CMCR register
Units
ns
ns
ns
ns
ns
ns
ns
ns
30ppm clock required for proper
operation of the TDM PLLs
C
C
13 MCLK < t
14 MCLK < t
C
C
~ 1 MCLK cycle
C
L
L
L
L
L
Test Conditions
= 75 pF
= 100 pF
= 75 pF
= 75 pF
= 75 pF
Test Conditions
Test Conditions
RACC
RACC
Data Sheet
< 16 MCLK
< 133 MCLK