MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 141

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 5204 + p*10 (Hex)
Label: CDDR_Pp (where p represents the port number)
Reset Value: 0000 (Hex)
Address: 5206 + p*10 (Hex)
Label: CSFSR_Pp (where p represents the port number)
Reset Value: 0000 (Hex)
Address: 5208 + p*10 (Hex)
Label: PLLEN_Pp (where p represents the port number)
Reset Value: 0001 (Hex)
RX_UNDERFLOW_ERROR
TX_UNDERFLOW_ERROR
RX_OVERFLOW_ERROR
TX_OVERFLOW_ERROR
DCO_DIFF
Reserved
Label
PLL_ENABLE
Reserved
Reserved
Label
Label
Position
15:12
11:0
Bit
Table 77 - Clocking DCO Difference Register (one per port)
Position
Position
Table 78 - SRTS FIFO Status Register (one per port)
15:4
15:1
Bit
Bit
0
1
2
3
0
Table 79 - PLL Enable Register (one per port)
Type
R/W
R/O
R/O/L
R/O/L
R/O/L
R/O/L
Frequency offset value.
When PLL_MODE_SEL (in register 5200h + p*10h) is set to CPU mode, the value in this
field is used to set the PLL output frequency directly, instead of using the filter output. In
CPU mode, the PLL input selected by PLL_INPUT_SEL (in register 5200h + p*10h) is no
longer used. Data read from this field is interpreted as 2’s complement format.
Always reads “0000”.
Type
Type
R/W
R/O
R/O
Zarlink Semiconductor Inc.
Receive SRTS FIFO Overflow Error.
Receive SRTS FIFO Underflow Error.
Transmit SRTS FIFO Overflow Error.
Transmit SRTS FIFO Underflow Error.
When cleared, the PLL for this port is held in reset.
If set, the Receive SRTS FIFO has overflowed. Writing a ‘0’ to this bit clears it.
If set, the Receive SRTS FIFO has underrun. Writing a ‘0’ to this bit clears it.
If set, the Transmit SRTS FIFO has overflowed. Writing a ‘0’ to this bit clears it.
If set, the Transmit SRTS FIFO has underrun. Writing a ‘0’ to this bit clears it.
Always reads “0000_0000_0000”.
Always reads “0000_0000_0000_000”.
MT90520
141
Description
Description
Description
Data Sheet