MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 143

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 6200 + p*10 (Hex)
Label: TDM1_Pp (where p represents the port number)
Reset Value: 0000 (Hex)
TDM_CLK_MODE
TDM_LINK_TYPE
TDM_CLK_RATE
LATENCY_LPBK
TDM_CLK_POL
TDM_PULSE_
TDM_PULSE_
TDM_DATA_
TDM_LOW_
TDM_BUS_
INT_LOS_
FORMAT
ENABLE
MODE
Label
POL
SEL
Position
14:13
Bit
10
11
12
15
5
6
7
8
9
Table 82 - TDM Control Register 1 (one per port)
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDM Frame Pulse Selection. (Applies only to SDT mode.)
‘0’ = STiMF pin is a frame pulse.
‘1’ = STiMF pin is a multiframe pulse.
In Backplane SDT mode, this bit must cleared.
TDM Frame Pulse Polarity. (Applies only to SDT mode.)
In Generic mode:
‘0’ = Negative polarity.
‘1’ = Positive polarity.
In ST-BUS mode, this bit must be cleared.
Segmentation TDM Input Clock Polarity.
‘0’ = TDM data is sampled on the rising edge.
‘1’ = TDM data is sampled on the falling edge.
In ST-BUS SDT mode, this bit must be set.
TDM Clock Rate.
‘0’ = TDM clock is 1.544 MHz.
‘1’ = TDM clock is 2.048 MHz or 4.096 MHz.
TDM Link Type.
‘0’ = E1 link.
‘1’ = DS1 link.
Internal LOS Enable (Applies only to UDT mode).
‘0’ = Internal version of LOS disabled.
‘1’ = Internal version of LOS enabled.
If this bit is set, the occurrence of an LOS event on the port will be propagated throughout
the device, possibly influencing the signals output on PRI_REF, PRI_LOS, and the port’s
SToCLK.
This bit must be set if TDM_LOS_CLK (bit<1>) is set.
TDM Clocking Mode. (Applies only to SDT mode; must be cleared in UDT mode.)
‘0’ = Independent mode (Independent clocks and frame pulses)
‘1’ = Backplane mode (Common clock and frame pulse)
TDM Bus Mode (Applies only to SDT mode; must be cleared in UDT mode.)
‘0’ = Generic.
‘1’ = ST-BUS. (The clock is 4.096 MHz.)
TDM Data Mode.
“00” = No cells generated from this port.
“01” = UDT mode
“10” = SDT mode.
“11” = SDT mode with N>46. This mode should be used when any VC associated with this
port has more than 46 channels.
Low latency loopback.
‘0’ = Normal operation.
‘1’ = Loopback data from DSTi to DSTo.
Note 1: If this bit is set, data from DSTi is output on DSTo, regardless of the value of the
TDM_REASS_PORT_CONTROL bit in TDM Control Register 3 (i.e., even if the port is
apparently inactive, loopback data will be output on DSTo).
Note 2: To use low-latency loopback, the clock edge used to sample the incoming TDM
data (determined by TDM_CLK_POL in this register) must be opposite to the clock edge
used to drive the outgoing TDM data (determined by TDM_REASS_CLK_POL, set at
6204h).
Note 3: The delay through the device in low latency loopback mode is approximately 2
TDM clock cycles.
Zarlink Semiconductor Inc.
MT90520
143
Description
Data Sheet