MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 145

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 6206 + p*10 (Hex)
Label: TDM4_Pp (where p represents the port number)
Reset Value: 0040 (Hex)
BUF_ERROR_SE
BUF_ERROR_SE
UNDER_STATUS
UNDER_STATUS
Address: 6208 + p*10 (Hex)
Label: TDM5_Pp (where p represents the port number)
Reset Value: 0000 (Hex)
UDT_TDM_OUT_
SDT_TDM_OUT_
UDT_TDM_OUT_
SDT_TDM_OUT_
SIMPLE_UNDER
RUN_REPORT
SDT_SIMPLE_
SDT_SIMPLE_
UDT_LOS_SE
BUF_STATUS
BUF_STATUS
SDT_PERM_
SDT_PERM_
UNDER_SE
UNDER_SE
UNDERRUN_
UDT_LOS_
Reserved
STATUS
REPORT
Label
PERM_
Label
Position
15:11
Position
Bit
10
0
1
2
3
4
5
6
7
8
9
15:0
Bit
Table 85 - TDM Control Register 4 (one per port)
Table 86 - TDM Control Register 5 (one per port)
R/O/L
R/O/L
R/O/L
R/O/L
R/O/L
Type
R/W
R/W
R/W
R/W
R/W
R/O
R/O
R/O/L
Type
Always reads ‘0’.
UDT Loss of Signal (LOS) Service Enable.
When this bit is set and UDT_LOS_STATUS is asserted, TDM_SRV is set in the Main
Status Register at 0002h.
UDT TDM Output Buffer Error Service Enable.
When this bit is set and UDT_TDM_OUT_BUF_STATUS is asserted, TDM_SRV is set in
the Main Status Register at 0002h.
SDT TDM Output Buffer Error Service Enable.
When this bit is set and SDT_TDM_OUT_BUF_STATUS is asserted, TDM_SRV is set in
the Main Status Register at 0002h.
SDT Permanent Underrun Service Enable.
When this bit is set and SDT_PERM_UNDER_STATUS is asserted, TDM_SRV is set in the
Main Status Register at 0002h.
SDT Simple Underrun Service Enable.
When this bit is set and SDT_SIMPLE_UNDER_STATUS is asserted, TDM_SRV is set in
the Main Status Register at 0002h.
UDT Loss of Signal (LOS) Status.
This bit is set when a loss of signal is detected on CSTi/LOSi. Writing a ‘0’ to this bit clears it.
This bit cannot be cleared until the TDM Control Register 1 is programmed.
UDT TDM Output Buffer Error Status.
This bit is set when there is an error in the UDT TDM output buffer. Writing a ‘0’ to this bit
clears it.
SDT TDM Output Buffer Error Status.
This bit is set when there is an error in the SDT TDM output buffer. Writing a ‘0’ to this bit
clears it.
SDT Permanent Underrun Status.
This bit is set when a permanent underrun service enable bit is set in the TDM SDT
Reassembly Control Structure for the port and the corresponding permanent underrun
condition occurs. Writing a ‘0’ to this bit clears it.
SDT Simple Underrun Status.
This bit is set when a simple underrun service enable bit is set in the TDM SDT Reassembly
Control Structure for the port and the corresponding simple underrun condition occurs.
Writing a ‘0’ to this bit clears it.
SDT Simple Underrun Report.
Indicates the TDM channel on which a “simple underrun” occurred last.
Permanent Underrun Report. (Applies only to SDT mode.)
This register represents bits<31:16> of the 32-bit permanent underrun report. Bit<31>
corresponds to channel 31, bit<30> corresponds to channel 30, etc.
When an underrun occurs on a certain channel, the corresponding bit is set high; the
microprocessor can clear these bits by writing them to ‘0’.
Zarlink Semiconductor Inc.
MT90520
145
Description
Description
Data Sheet