MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 21

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

V3, U1, P3, N2,
AC3, AB2, W4,
AE1,AB3, AA2,
AD2, AA4, V5,
AA1, W2, R4,
AB1, Y2, T5,
U4, U2, R1,
AC4,Y5, Y3,
W1,U3, R2,
W3, T4, T1,
T3, P4, M1
R3, N4, L2
AD3, AC1,
AF2, AD1,
Ball Pin #
N1, K1
N3, L3
M5, L1
K2
CSTi/LOSi[7:0]
SToCLK[7:0]
STiCLK[7:0]
SToMF[7:0]
STiMF[7:0]
Pin Name
DSTi[7:0]
I/O
O
O
I
I
I
I
Table 3 - TDM Port Pins
CMOS PD
CMOS PD
CMOS PD
CMOS PD
Zarlink Semiconductor Inc.
3.3 V,
3.3 V,
3.3 V
3.3 V
3.3 V
3.3 V
4 mA
4 mA
Type
MT90520
21
PCM Input Clocks.
These inputs are used to sample the incoming PCM
data/CAS from the E1 or DS1 lines.
In Structured CES mode, ST-BUS format STiCLK is
4.096 MHz; Generic format STiCLK is 1.544 MHz or
2.048 MHz for DS1; or 2.048 MHz for E1.
In Unstructured CES mode, these pins accept
1.544 MHz for DS1 or 2.048 MHz for E1.
Input Frame Pulses.
In Structured CES mode, these pins are input frame
pulses which set the frame boundaries for the incoming
data and CAS. These signals can be either multiframe
or frame inputs.
Not used in Unstructured CES mode.
Serial PCM Data Inputs.
In Unstructured CES mode, each pin carries a
1.544 Mbps or 2.048 Mbps serial stream.
In Structured CES mode, each pin carries a
1.544 Mbps or 2.048 Mbps serial stream which
contains a 24-channel data stream in DS1 operation or
a 32-channel data stream in E1 operation.
Serial PCM Signalling Inputs or Input Loss of Signal
(LOS) Indicators.
In Structured CES mode, these pins carry CAS
signalling inputs.
In Unstructured CES mode, these pins input LOS
signals from external LIUs.
PCM Output Clocks.
These outputs are used to drive the PCM data/CAS out
to the E1 or DS1 lines.
In Structured CES mode, ST-BUS format SToCLK is
4.096 MHz; Generic format SToCLK is 1.544 MHz or
2.048 MHz for DS1; or 2.048 MHz for E1.
In Unstructured CES mode, these pins provide
1.544 MHz for DS1 or 2.048 MHz for E1.
Output Frame Pulses.
In Structured CES mode, these pins are output frame
pulses which set the frame boundaries for the outgoing
data and CAS. These signals are programmable as
either multiframe pulses or frame pulses.
Not used in Unstructured CES mode.
Description
Data Sheet