MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 39

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.2
The external memory interface module of the MT90520 provides access to external memory devices by various
MT90520 modules (i.e., TDM, TX_SAR, UTOPIA, SDT RX_SAR, Data RX_SAR) and by the CPU.
The MT90520 can interface with both the pipelined and flow-through types of synchronous zero bus turnaround
(ZBT) RAM. The difference between flow-through and pipelined memories is illustrated in Figure 8 and Figure 9. In
the case of flow-through memory, read cycle data is available on the next rising clock edge after the address is
sampled by the memory. Contrarily, the data from pipelined memory is available two rising clock edges after the
address is sampled by the memory. A flow-through write cycle requires that valid data be placed on the data bus
before the next rising clock edge after the address is sampled. On the other hand, data must be valid before the
second rising edge of the clock after the address is presented to memory in the case of pipelined RAM.
CLOCK
ADDRESS
DATA
CLOCK
ADDRESS
DATA
External Memory Interface
Note: The number of clock cycles between an address (ADDRESS1) and its read data (DATA1) is
set according to the MTYP field in the Memory Arbiter Configuration Register at byte address
7000h.
Note: The number of clock cycles between an address (ADDRESS1) and its written data
(DATA1) is set according to the MTYP field in the Memory Arbiter Configuration Register at byte
address 7000h.
ADDRESS1
ADDRESS1
Figure 8 - Memory Read Pipeline Length
Figure 9 - Memory Write Pipeline Length
Zarlink Semiconductor Inc.
MT90520
ADDRESS2
ADDRESS2
39
DATA1
DATA1
DATA1
DATA1
Data Sheet