MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 16

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.8
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2.9
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2.10
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2.10.1
2.10.1.1
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2.10.1.2
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2.10.1.3
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2.10.1.4
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2.10.1.5
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Per-port TDM_in to TDM_out low-latency loopback (DSTi input stream to DSTo output stream)
Per-port TDM_in to TDM_out loopback through the Segmentation and Reassembly Circular Buffers in
external memory (SDT mode only)
Flexible, multi-stream, per-channel TDM circular-buffer loopback possible in SDT Backplane mode
Loopback provided from incoming UTOPIA FIFO to outgoing UTOPIA FIFO (with or without filtering by
Match and Match Enable registers)
Master clock (MCLK) rate of 66.0 MHz
2.5 Volt core supply and 3.3 Volt I/O supply (5 V tolerant I/Os)
Power consumption: 1.9 W
IEEE 1149 (JTAG) Boundary-Scan Test Access Port
456-pin Plastic BGA
-40°C to +85°C (industrial temperature range)
Wide variety of interrupt source bits, allowing for easy monitoring of MT90520 operation
Associated enable bits which enable or disable assertion of the service request and, ultimately, the IRQ
interrupt pin
External Memory Read Parity Error Alarm
Per-port Loss of Signal Alarm (UDT mode only)
Per-port UDT TDM Output Buffer Error Alarm (UDT mode only)
Per-port SDT TDM Output Buffer Error Alarm (SDT mode only)
Per-port Simple Underrun Error Alarm (SDT mode only)
Per-port Permanent Underrun Error Alarm (SDT mode only)
UTOPIA Incoming Cell Counter Rollover
Incoming Parity Mismatches Counter Rollover
Data TX_SAR - Transmit Non-CBR Data Cell Buffer Empty Alarm
Reassembled Cell Counter Rollover
AAL1-byte Header Error (i.e., CRC and/or Parity Error) Counter Rollover
AAL1-byte Sequence Error Counter Rollover
Testing Modes
Miscellaneous
Interrupts
Module Level Service Requests
External Memory Interface Module
TDM Module
UTOPIA Module
TX_SAR Module
UDT RX_SAR Module
Zarlink Semiconductor Inc.
MT90520
16
Data Sheet