MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 161

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

7.2.4
7.2.4.1
UTO_IN_CLK Period
UTO_IN_CLK Pulse Width (HIGH / LOW)
Input Setup Time -
(UTO_IN_CLAVATM_ENBPHY, UTO_IN_SOC
asserted and UTO_IN_DATA[7:0] VALID) to
UTO_IN_CLK rising
Input Hold Time - UTO_IN_CLK rising to
(UTO_IN_DATA[7:0] INVALID and UTO_IN_SOC
and UTO_IN_CLAVATM_ENBPHY de-asserted)
Output Delay - UTO_IN_CLK rising to
UTO_IN_ENBATM_CLAVPHY asserted
Output Hold Time - UTO_IN_CLK rising to
UTO_IN_ENBATM_CLAVPHY de-asserted
Note: The MT90520 operates with the UTOPIA cell-level handshake.
SToCLK or C4M/C2M
2.048 MHz (Generic)
SToCLK or C4M/C2M
4.096 MHz (ST-BUS)
DSTo1/CSTo1
DSTo2/CSTo2
SToMF/F0
SToCLK or C4M/C2M
4.096 MHz
DSTo/CSTo
Table 98 - UTOPIA Level 1 Interface Timing - ATM mode - Incoming Data (UTOPIA RX Bus)
UTOPIA Interface
UTOPIA Level 1
Characteristic
Bit 0, Last Channel
Figure 59 - TDM Bus Output Clocking Parameters - ST-BUS
t
FPD
Valid Data
Valid Data
Figure 60 - TDM Bus Outputs - Serial Output Timing
t
SODX
t
t
FPW
SODZ
Bit 7, Channel 0
t
URX1H/L
t
t
t
t
t
Sym.
URX1P
URXIS
URXIH
URXD
URXH
Zarlink Semiconductor Inc.
Valid Data
High-Z
t
SODV
MT90520
t
SODV
19.23
Min.
7.7
161
4
1
1
Bit 6, Channel 0
t
URX1P
Typ.
Valid Data
High-Z
t
/2
SOZX
Max
13.8
t
SToCK
.
Bit 5, Channel 0
Units
ns
ns
ns
ns
ns
ns
Valid Data
Valid Data
t
SToCKH
UTO_IN_CLK = 52 MHz
C
C
L
L
t
=20 pF; UTO_IN_CLK < 52 MHz
=20 pF; UTO_IN_CLK < 52 MHz
SToCKL
Test Conditions
Bit 4, Channel 0
Data Sheet
V
V
V
V
TT
TT
TT
TT
V
V
V
TT
TT
TT