MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 166
MT90520AG
Manufacturer Part Number
MT90520AG
Description
8-Port Primary Rate Circuit Emulation AAL1 SAR
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.MT90520AG.pdf
(180 pages)
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UTO_IN_DATA[15:0]
See Note 2
UTO_IN_ADDR[4:0]
See Note 1
UTO_IN_ENBATM
_CLAVPHY
UTO_IN_CLAVAT
M_ENBPHY
UTO_IN_SOC
UTO_IN_CLK
Drive to High-Z - UTO_IN_CLK rising to
UTO_IN_ENBATM_CLAVPHY HIGH-Z
High-Z to Drive - UTO_IN_CLK rising and
UTO_IN_ENBATM_CLAVPHY HIGH-Z to
UTO_IN_ENBATM_CLAVPHY change
UTO_OUT_CLK Period
UTO_OUT_CLK Pulse Width (HIGH / LOW)
Input Setup Time -
(UTO_OUT_CLAVATM_ENBPHY asserted
and UTO_OUT_ADDR[4:0] VALID) to
UTO_OUT_CLK rising
Input Hold Time - UTO_IN_CLK rising to
(UTO_OUT_ADDR[4:0] INVALID and
UTO_OUT_CLAVATM_ENBPHY de-asserted)
Output Delay - UTO_OUT_CLK rising to
(UTO_OUT_ENBATM_CLAVPHY,
UTO_OUT_SOC asserted and
UTO_OUT_DATA[15:0] VALID)
Note 2: UTO_IN_DATA is a 16-bit bus; therefore, P24 indicates the last cell payload word to be transmitted.
Note 1: M is the address of the MT90520; N is the address of another PHY device, where N is not equal to M. An
address of 1Fh (31d) indicates a null PHY port.
Table 103 - UTOPIA Level 2 Interface Timing - PHY mode - Outgoing Data (UTOPIA RX Bus)
Table 102 - UTOPIA Level 2 Interface Timing - PHY mode - Incoming Data (UTOPIA TX Bus)
Figure 65 - UTOPIA Level 2 Interface Timing - PHY Mode - Incoming Data (UTOPIA TX Bus)
Characteristic
Characteristic
t
t
UTXD
UTXZX
t
UTX2P
M
1F
X
N
t
URX2H/L
t
1F
t
t
t
Sym.
URX2P
URXIH
t
URXIS
URXD
UTXIS
t
t
Sym.
UTXDZ
UTXZX
Zarlink Semiconductor Inc.
t
UTXIS
M
MT90520
19.23
Min.
7.7
t
t
4
1
UTXIH
UTXIS
Min.
1
1
1
1
H1
1F
166
t
URX2P
t
t
Typ.
UTXIH
UTXH
t
t
UTX2H
UTXDZ
H2
t
UTXIH
Typ.
N
/2
t
UTX2L
H3
1F
Max.
13.5
20.5
Max.
17.5
28.5
P1
N
Units
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
UTO_OUT_CLK = 52 MHz
C
MHz
C
MHz
L
L
C
C
C
C
= 40 pF; UTO_OUT_CLK < 52
= 80 pF; UTO_OUT_CLK < 33
L
L
L
L
=40 pF; UTO_IN_CLK < 52 MHz
=80 pF; UTO_IN_CLK < 33 MHz
=40 pF; UTO_IN_CLK < 52 MHz
=80 pF; UTO_IN_CLK < 33 MHz
P23
N
Test Conditions
Test Conditions
P24
1F
t
UTXIS
N
Data Sheet
t
UTXIH
X
V
V
V
V
V
V
TT
TT
TT
TT
TT
TT
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