HD6412350 Hitachi, HD6412350 Datasheet - Page 540
HD6412350
Manufacturer Part Number
HD6412350
Description
(HD6412350 / HD6432351) 16-BIT MICROCONTROLLER
Manufacturer
Hitachi
Datasheet
1.HD6412350.pdf
(989 pages)
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Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by dividing the system clock (ø), for input to TCNT.
Bit 2
CKS2
0
1
Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow
12.2.3
RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal
reset signal caused by overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
520
Bit
Initial value
R/W
Note: * Can only be written with 0 for flag clearing.
occurs.
see section 12.2.4, Notes on Register Access.
Bit 1
CKS1
0
1
0
1
Reset Control/Status Register (RSTCSR)
:
:
:
R/(W)*
WOVF
Bit 0
CKS0
0
1
0
1
0
1
0
1
7
0
RSTE
R/W
Description
Clock
ø/2 (initial value)
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
6
0
RSTS
R/W
5
0
Overflow Period (when ø = 20 MHz)*
25.6 µs
819.2 µs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
—
—
4
1
—
—
3
1
—
—
2
1
—
—
1
1
—
—
0
1
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