HD6412350 Hitachi, HD6412350 Datasheet - Page 156

• Manufacturer Part Number: HD6412350
• Description: (HD6412350 / HD6432351) 16-BIT MICROCONTROLLER
• Manufacturer: Hitachi

Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the
shift to the lower half of the row address in row address/column address multiplexing for the
DRAM interface. In burst operation on the DRAM interface, these bits also select the row address
to be used for comparison.
Bit 3
MXC1
0
1
Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the
number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This
setting is used for all areas designated as DRAM space. Wait input by the WAIT pin is disabled.
Bit 1
RLW1
0
1
136
Bit 2
MXC0
0
1
0
1
Bit 0
RLW0
0
1
0
1
Description
8-bit shift
9-bit shift
10-bit shift
—
Description
No wait state inserted
1 wait state inserted
2 wait states inserted
3 wait states inserted
When 8-bit access space is designated: Row address A
for comparison
When 16-bit access space is designated: Row address A
for comparison
When 8-bit access space is designated: Row address A
for comparison
When 16-bit access space is designated: Row address A
for comparison
for comparison
When 16-bit access space is designated: Row address A
for comparison
When 8-bit access space is designated: Row address A
23
23
23
23
23
23
(Initial value)
(Initial value)
to A
to A
to A
to A
to A
to A
8
9
10
9
10
11
used
used
used
used
used
used