HD6412350 Hitachi, HD6412350 Datasheet - Page 201

• Manufacturer Part Number: HD6412350
• Description: (HD6412350 / HD6432351) 16-BIT MICROCONTROLLER
• Manufacturer: Hitachi

(3) Relationship between Chip Select (CS) Signal and Read (RD) Signal
Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 6-33.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
(4) Usage Notes
When DRAM space is accessed, the ICIS0 and ICIS1 bit settings are disabled. In the case of
consecutive reads between different areas, for example, if the second access is a DRAM access,
only a T
However, in burst access in RAS down mode these settings are enabled, and an idle cycle is
inserted. The timing in this case is shown in figures 6-35 (a) and (b).
Address bus
CS (area A)
CS (area B)
p
RD
Possibility of overlap between
CS (area B) and RD
cycle is inserted, and a T
ø
Figure 6-33 Relationship between Chip Select (CS) and Read (RD)
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
T
2
T
3
Bus cycle B
T
I
1
cycle is not. The timing in this case is shown in figure 6-34.
T
2
Address bus
CS (area A)
CS (area B)
RD
ø
T
1
Bus cycle A
(b) Idle cycle inserted
T
(Initial value ICIS1 = 1)
2
T
3
T
I
Bus cycle B
T
1
T
2
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