HD6412350 Hitachi, HD6412350 Datasheet - Page 180

• Manufacturer Part Number: HD6412350
• Description: (HD6412350 / HD6432351) 16-BIT MICROCONTROLLER
• Manufacturer: Hitachi

6.5
6.5.1
When the H8S/2350 Series is in advanced mode, external space areas 2 to 5 can be designated as
DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be
directly connected to the H8S/2350 Series. A DRAM space of 2, 4, or 8 Mbytes can be set by
means of bits RMTS2 to RMTS0 in BCRH. Burst operation is also possible, using fast page mode.
6.5.2
Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in BCRH. The
relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6-5.
Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), and four areas
(areas 2 to 5).
Table 6-5
RMTS2
0
6.5.3
With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table 6-6
shows the relation between the settings of MXC1 and MXC0 and the shift size.
Table 6-6
Row
address
Column
address
160
MXC1 MXC0 Size
0
1
—
DRAM Interface
Overview
Setting DRAM Space
Address Multiplexing
RMTS1
0
1
MCR
Settings of Bits RMTS2 to RMTS0 and Corresponding DRAM Spaces
Address Multiplexing Settings by Bits MXC1 and MXC0
0
1
0
1
—
Shift
8 bits
9 bits
10 bits
Setting
prohibited
—
RMTS0
1
0
1
A
A
A
A
—
A
23
23
23
23
23
Area 5
Normal space
Normal space
DRAM space
to A
to A
to A
to A
to A
13
13
13
13
13
A
A
A
A
— — — — — — — — — — — — —
A
12
20
12
12
12
A
A
A
A
A
11
19
20
11
11
A
A
A
A
A
10
18
19
20
10
Area 4
A
A
A
A
A
9
17
18
19
9
Address Pins
A
A
A
A
A
8
16
17
18
8
A
A
A
A
A
7
15
16
17
7
Area 3
DRAM space
A
A
A
A
A
6
14
15
16
6
A
A
A
A
A
5
13
14
15
5
A
A
A
A
A
4
12
13
14
4
A
A
A
A
A
3
11
12
13
3
Area 2
DRAM space
A
A
A
A
A
2
10
11
12
2
A
A
A
A
A
1
9
10
11
1
A
A
A
A
A
0
8
9
10
0