HD6412350 Hitachi, HD6412350 Datasheet - Page 194
HD6412350
Manufacturer Part Number
HD6412350
Description
(HD6412350 / HD6432351) 16-BIT MICROCONTROLLER
Manufacturer
Hitachi
Datasheet
1.HD6412350.pdf
(989 pages)
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6.6
When burst mode is selected with the DRAM interface, the DACK output timing can be selected
with the DDS bit. When DRAM space is accessed in DMAC single address mode at the same
time, whether or not burst access is to be performed is selected.
6.6.1
Burst access is performed by determining the address only, irrespective of the bus master. The
DACK output goes low from the T
Figure 6-28 shows the DACK output timing for the DRAM interface when DDS = 1.
174
Figure 6-28 DACK Output Timing when DDS = 1 (Example of DRAM Access)
DMAC Single Address Mode and DRAM Interface
When DDS = 1
Read
Write
LCAS (LCAS)
CAS, (UCAS)
HWR, (WE)
HWR, (WE)
CSn (RAS)
D
D
A
15
15
23
DACK
to D
to D
to A
ø
0
0
0
C1
state in the case of the DRAM interface.
T
p
Row
T
r
T
c1
Column
T
c2
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