OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 73

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OX16PCI952-TQAG

Manufacturer Part Number
OX16PCI952-TQAG
Description
Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
Manufacturer
OXFORD [Oxford Semiconductor]
Datasheet

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PCI CLK no
1
6
9-10
10
11
14-15
17
18
Tstb (PCI clk to valid STB_N)
Tpd (PCI clk to valid port Address) - 16ns max*
ECP Forward Transfer Cycle duration is dependant upon the timing response of the peripheral’s BUSY line and the parallel port
filters. Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the
host to the peripheral’s BUSY line when the filters are enabled.
* These values exclude the effects of external parasitic (board) capacitances.
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
- Start of 1
- Start of 1
- 1
- Peripheral Asserts BUSY in response to the host driving STB_N low
- Start of 2
- Host responds to BUSY by de-asserting STB_N (2 clock cycles after sampling BUSY) – 1
- Peripheral Deasserts BUSY
- End of 1
Start of 2nd ECP forward Transfer Cycle
st
PCI transaction terminates with a “Data Transfer”
st
st
st
nd
ECP forward transfer (2 clock cycles after sampling BUSY)
PCI write to ECP DFIFO register
PCI write to ECP DFIFO register. Current ECP forward transfer remains unaffected.
ECP forward Transfer Cycle
- 16ns max*
2 Consecutive Write Transactions to ECP DFIFO
External-Free Release
st
ECP forward transfer.
OX16PCI952
Page 73

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