OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 53

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

8
8.1
The OX16PCI952 offers a compact, low power, IEEE-1284
compliant host-interface parallel port, designed to interface
to many peripherals such as printers, scanners and
external drives. It supports compatibility modes, SPP,
NIBBLE, PS2, EPP and ECP modes. The register set is
compatible with the Microsoft® register definition.
The system can access the parallel port registers via two
blocks of I/O space as defined by 2 BARs (Base Address
Registers) in the PCI Configuration space of function
1(dual-mode device operation only). BAR0 (8-bytes of I/O
space) contains the address of the basic parallel port
registers and BAR1 (4-bytes of I/O space) contains the
address of the upper (extended) registers. These register
blocks are referred to as the ‘lower block’ and ‘upper block’,
respectively, in this section.
If the upper block is located at an address 0x400 above the
lower block, as shown below, then generic PC parallel port
device drivers can be used to configure the port, as the
addressable registers of legacy parallel ports always have
this relationship.
If this relationship is not used, then a custom driver will be
needed.
8.1.1
SPP (output-only) mode is the standard implementation of
a simple parallel port, and is the default mode of the
OX16PCI952 following a reset.
In this mode, the parallel port data lines (PD[7:0] lines)
always drive the value written to the PDR register. All data
transfers are done under software control using the
registers DCR and DSR. Input must be performed in nibble
mode.
Generic device driver-software may use the address in I/O
space defined by BAR0 (of function 1) to access these
parallel port registers.
8.1.2
This mode is also referred to as bi-directional or compatible
parallel port. To use the PS2 mode, the mode field of the
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
BAR0 = 0x00000379 (8 bytes of I/O at address 0x378)
BAR1 = 0x00000779 (4 bytes of I/O at address 0x778)
B
Operation and Mode selection
I
-
DIRECTIONAL
SPP mode
PS2 mode
P
ARALLEL
P
ORT
External-Free Release
Extended Control Register (ECR[7:5]) must be set to ‘001’,
using the negotiation steps as defined by the IEEE1284
specification.
PS2 operation is similar to SPP mode but, in this mode,
directional control of the parallel port data lines (PD[7:0]) is
possible by setting & clearing DCR[5], the data direction
bit.
8.1.3
To use the Enhanced Parallel Port (‘EPP’) mode, the mode
field of the Extended Control Register (ECR[7:5]) must be
set to ‘100’ using the negotiation steps as defined by the
IEEE1284 specification
The EPP address and data port registers are compatible
with the IEEE 1284 definition. A write or read to one of the
EPP port registers is passed through the parallel port to
access the external peripheral.
In EPP mode, the STB#, INIT#, AFD# AND SLIN# pins
change from open-drain outputs to active push-pull (totem
pole) drivers (as required by IEEE 1284) and the pins
ACK#, AFD#, BUSY, SLIN# and STB# are redefined as
INTR#, DATASTB#, WAIT#, ADDRSTB# and WRITE#
respectively.
An EPP port access begins with the host reading or writing
to one of the EPP port registers. The device automatically
buffers the data between the I/O registers and the parallel
port depending on whether it is a read or a write cycle.
When the peripheral is ready to complete the transfer it
takes the WAIT# status line high. This allows the host to
complete the EPP cycle.
If a faulty or disconnected peripheral failed to respond to an
EPP cycle the host would never see a rising edge on
WAIT#, and subsequently lock up. A built-in time-out facility
is provided in order to prevent this from happening. It uses
a fixed internal timer which aborts the EPP cycle and sets a
flag in the DSR register to indicate the condition. When the
parallel port is not in EPP mode the timer is switched off to
reduce current consumption. The host time-out period is
10μs as specified with the IEEE-1284 specification.
The register set is compatible with the Microsoft® register
definition. Assuming that the upper block is located 400h
above the lower block, the EPP registers are found at
offset 000-007h and 400-402h.
EPP mode
OX16PCI952
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