OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 38

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

LCR[5:3]: Parity type
The selected parity type will be generated during
transmission and checked by the receiver, which may
produce a parity error as a result. In 9-bit mode parity is
disabled and LCR[5:3] is ignored.
LCR[6]: Transmission break
logic 0 ⇒ Break transmission disabled.
logic 1 ⇒ Forces the transmitter data output SOUT low to
alert the communication terminal, or send zeros in IrDA
mode.
It is the responsibility of the software driver to ensure that
the break duration is longer than the character period for it
to be recognised remotely as a break rather than data.
LCR[7]: Divisor latch enable
logic 0 ⇒ Access to DLL and DLM registers disabled.
logic 1 ⇒ Access to DLL and DLM registers enabled.
7.5.3
This register provides the status of data transfer to CPU.
LSR[0]: RHR data available
logic 0 ⇒ RHR is empty: no data available
logic 1 ⇒ RHR is not empty: data is available to be read.
LSR[1]: RHR overrun error
logic 0 ⇒ No overrun error.
logic 1 ⇒ Data was received when the RHR was full. An
LSR[2]: Received data parity error
logic 0 ⇒ No parity error in normal mode or 9
logic 1 ⇒ Data has been received that did not have
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
LCR[5:3]
Line Status Register ‘LSR’
Table 18: LCR Parity Configuration
001
011
101
111
overrun error has occurred. The error is flagged
when the data would normally have been
transferred to the RHR.
received data is ‘0’ in 9-bit mode.
correct parity in normal mode or 9
received data is ‘1’ in 9-bit mode.
xx0
Parity bit forced to 1
Parity bit forced to 0
Even parity bit
Odd parity bit
No parity bit
Parity type
th
th
External-Free Release
bit of
bit of
The Parity error flag will be set when the data item in error
is at the top of the RHR and cleared following a read of the
LSR. In 9-bit mode LSR[2] is no longer a flag and
corresponds to the 9
LSR[3]: Received data framing error
logic 0 ⇒ No framing error.
logic 1 ⇒ Data has been received with an invalid stop bit.
This status bit is set and cleared in the same manner as
LSR[2]. When a framing error occurs, the UART will try to
re-synchronise by assuming that the error was due to
sampling the start bit of the next data item.
LSR[4]: Received break error
logic 0 ⇒ No receiver break error.
logic 1 ⇒ The receiver received a break.
A break condition occurs when the SIN line goes low
(normally signifying a start bit) and stays low throughout
the start, data, parity and first stop bit. (Note that the SIN
line is sampled at the bit rate). One zero character with
associated break flag set will be transferred to the RHR
and the receiver will then wait until the SIN line returns
high. The LSR[4] break flag will be set when this data item
gets to the top of the RHR and it is cleared following a read
of the LSR.
LSR[5]: THR empty
logic 0 ⇒ Transmitter FIFO (THR) is not empty.
logic 1 ⇒ Transmitter FIFO (THR) is empty.
LSR[6]: Transmitter and THR empty
logic 0 ⇒ The transmitter is not idle
logic 1 ⇒ THR is empty and the transmitter has
LSR[7]: Receiver data error
logic 0 ⇒ Either there are no receiver data errors in the
logic 1 ⇒ At least one parity error, framing error or break
In 450 mode LSR[7] is permanently cleared, otherwise this
bit will be set when an erroneous character is transferred
from the receiver to the RHR. It is cleared when the LSR is
read. Note that in 16C550 this bit is only cleared when
all of the erroneous data are removed from the FIFO. In
9-bit data framing mode parity is permanently disabled, so
this bit is not affected by LSR[2].
completed the character in shift register and is
in idle mode. (I.e. set whenever the transmitter
shift register and the THR are both empty.)
FIFO or it was cleared by a read of LSR.
indication in the FIFO.
th
bit of the received data in RHR.
OX16PCI952
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