OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 57

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

8.3.7
Hardware transfers data from this 16-bytes deep FIFO to
the peripheral when DCR(5) = ‘0’. When DCR(5) = ‘1’
hardware transfers data from the peripheral to this FIFO.
8.3.8
Used by the software in conjunction with the full and empty
flags to determine the depth of the FIFO and interrupt
levels.
8.3.9
ECR[7:5] must be set to ‘111’ to access this register.
Interrupts generated will always be level, and the ECP port
only supports an impID of ‘001’.
8.3.10 Configuration B register
ECR[7:5] must be set to ‘111’ to access this register. Read
only, all bits will be set to 0, except for bit[6] which will
reflect the state of the interrupt.
8.3.11 Extended control register ‘ECR’
The Extended control register is located at offset 002h in
upper block. It is used to configure the operation of the
parallel port.
ECR[4:0]: Reserved - write
These bits are reserved and must always be set to
“00001”.
ECR[0]: Empty - read
When DCR[5} = ‘0’
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
ECP Data FIFO
Test FIFO
Configuration A register
External-Free Release
logic 0 ⇒ FIFO contains at least one byte
logic 1 ⇒ FIFO completely empty
When DCR[5} = ‘1’
logic 0 ⇒ FIFO contains at least one byte
logic 1 ⇒ FIFO contains less than one byte
ECR[1]: Full - read
When DCR[5} = ‘0’
logic 0 ⇒ FIFO has at least one free byte
FIFO completely full
When DCR[5} = ‘1’
logic 0 ⇒ FIFO has at least one free byte
logic 1 ⇒ FIFO full
ECR[2]: serviceIntr - read
When DCR[5} = ‘0’
logic 1 ⇒ writeIntrThreshold (8) free bytes or more in
FIFO
When DCR[5} = ‘1’
logic 1 ⇒ readIntrThreshold (8) bytes or more in FIFO
ECR[7:5]: Mode – read / write
These bits define the operational mode of the parallel port.
logic ‘000’
logic ‘001’
logic ‘010’
logic ‘011’
logic ‘100’
logic ‘101’
logic ‘110’
logic ‘111’
SPP
PS2
Reserved
ECR
EPP
Reserved
Test
Config
OX16PCI952
Page 57