OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 41

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

Level 6:
CTS or RTS changed interrupt (ISR[5:0]=’100000’):
This interrupt is set whenever any of the CTS# or RTS#
pins changes state from low to high. It is cleared on an ISR
read of a level 6 interrupt.
7.6.4
For a channel to go into sleep mode, all of the following
conditions must be met:
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7.7
7.7.1
MCR[0]: DTR
logic 0 ⇒ Force DTR# output to inactive (high).
logic 1 ⇒ Force DTR# output to active (low).
Note that DTR# can be used for automatic out-of-band flow
control when enabled using ACR[4:3] (see section 7.11.3).
MCR[1]: RTS
logic 0 ⇒ Force RTS# output to inactive (high).
logic 1 ⇒ Force RTS# output to active (low).
Note that RTS# can be used for automatic out-of-band flow
control when enabled using EFR[6] (see section 7.9.4).
MCR[2]: OUT1
logic 0 ⇒ Force OUT1# output low when loopback mode
logic 1 ⇒ Force OUT1# output high.
MCR[3]: OUT2/External interrupt enable
logic 0 ⇒ Force OUT2# output low when loopback mode
logic 1 ⇒ Force OUT2# output high. If INT_SEL# is low
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
Sleep mode enabled (IER[4]=1 in 650/950 modes, or
IER[5]=1 in 750 mode):
The transmitter is idle, i.e. the transmitter shift register
and FIFO are both empty.
SIN is high.
The receiver is idle.
The receiver FIFO is empty (LSR[0]=0).
Modem Interface
Sleep Mode
Modem Control Register ‘MCR’
is disabled.
is disabled. If INT_SEL# is low the external
interrupt is in high-impedance state when
MCR[3] is cleared. If INT_SEL# is high MCR[3]
does not affect the interrupt.
the external interrupt is enabled and operating
in normal active (forcing) mode when MCR[3] is
high. If INT_SEL# is high MCR[3] does not
affect the interrupt.
External-Free Release
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A read of IER[4] (or IER[5] if a 1 was written to that bit
instead) shows whether the power-down request was
successful. The UART will retain its programmed state
whilst in power-down mode.
The channel will automatically exit power-down mode when
any of the conditions 1 to 7 becomes false. It may be
woken manually by clearing IER[4] (or IER[5] if
alternate sleep mode is enabled).
Sleep mode operation is not available in IrDA mode.
MCR[4]: Loopback mode
logic 0 ⇒ Normal operating mode.
logic 1 ⇒ Enable local loop-back mode (diagnostics).
In local loop-back mode, the transmitter output (SOUT) and
the four modem outputs (DTR#, RTS#, OUT1# and
OUT2#) are set in-active (high), and the receiver inputs
SIN, CTS#, DSR#, DCD#, and RI# are all disabled.
Internally the transmitter output is connected to the receiver
input and DTR#, RTS#, OUT1# and OUT2# are connected
to modem status inputs DSR#, CTS#, RI# and DCD#
respectively.
In this mode, the receiver and transmitter interrupts are
fully operational. The modem control interrupts are also
operational, but the interrupt sources are now the lower
four bits of the Modem Control Register instead of the four
modem status inputs. The interrupts are still controlled by
the IER.
MCR[5]: Enable XON-Any in Enhanced mode or enable
out-of-band flow control in non-Enhanced mode
650/950 (enhanced) modes:
logic 0 ⇒ XON-Any is disabled.
logic 1 ⇒ XON-Any is enabled.
In enhanced mode (EFR[4]=1), this bit enables the Xon-
Any operation. When Xon-Any is enabled, any received
data will be accepted as a valid XON (see in-band flow
control, section 7.9.3).
The UART is not in loopback mode (MCR[4]=0).
Changes on modem input lines have been
acknowledged (i.e. MSR[3:0]=0000).
No interrupts are pending.
OX16PCI952
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